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? semiconductor components industries, llc, 2016 november, 2017 ? rev. 4 1 publication order number: noip1sn1300a/d noip1sn1300a python 1.3/0.5/0.3 megapixels global shutter cmos image sensors features ? size options: ? python 300: 640 x 480 active pixels, 1/4? optical format ? python 500: 800 x 600 active pixels, 1/3.6? optical format ? python 1300: 1280 x 1024 active pixels, 1/2? optical format ? data output options: ? p1?sn/se/fn: 4 l vds data channels ? p2?sn/se: 10 bit parallel ? p3?sn/se/fn: 2 l vds data channels ? 4.8 m x 4.8 m low noise global shutter pixels with in-pixel cds ? monochrome (sn), color (se) and nir (fn) ? zero row overhead time (zrot) mode enabling higher frame rate ? frame rate at full resolution, 4 lvds data channels (p1?sn/se/fn only) ? 210/165 frames per second @ sxga (zrot/nrot) ? 545/385 frames per second @ svga (zrot/nrot) ? 815/545 frames per second @ vga (zrot/nrot) ? frames rate at full resolution (cmos) ? 50/43 frames per second @ sxga (zrot/nrot) ? on?chip 10?bit analog?to?digital converter (adc) ? four/two/one lvds high speed serial outputs or parallel cmos output ? random programmable region of interest (roi) readout ? serial peripheral interface (spi) ? automatic exposure control (aec) ? phase locked loop (pll) ? high dynamic range (hdr) modes possible ? dual power supply (3.3 v and 1.8 v) ? ?40 c to +85 c operational temperature range ? 48?pin lcc ? power dissipation: ? 620 mw (p1, 4 lvds, zrot) ? 420 mw (p1, p3, 2 lvds, nrot) ? 270 mw (p1, p3, 1 lvds, nrot) ? 420 mw (p2, zrot) ? these devices are pb?free and are rohs compliant applications ? machine vision ? motion monitoring ? security ? barcode scanning (2d) description the python 300, python 500, and python 1300 image sensors utilize high sensitivity 4.8 m x 4.8 m pixels that support low noise ?pipelined? and ?triggered? global shutter readout modes. the sensors support correlated double sampling (cds) readout, reducing noise and increasing dynamic range. the image sensors have on?chip programmable gain amplifiers and 10?bit a/d converters. the integration time and gain parameters can be reconfigured without any visible image artifact. optionally the on?chip automatic exposure control loop (aec) controls these parameters dynamically. the image?s black level is either calibrated automatically or can be adjusted by adding a user programmable offset. a high level of programmability using a four wire serial peripheral interface enables the user to read out specific regions of interest. up to eight regions can be programmed, achieving even higher frame rates. the image data interface of the p1?sn/se/fn devices consists of four lvds lanes, enabling frame rates up to 210 frames per second in zero rot mode for the python 1300. each channel runs at 720 mbps. a separate synchronization channel containing payload information is provided to facilitate the image reconstruction at the receiving end. the p2?sn/se devices provide a parallel cmos output interface at reduced frame rate. the p3?sn/se/fn devices are the same as the p1?sn/se/fn but with only two of the four lvds data channels enabled, facilitating frame rates of 90 frames per second in normal rot for the python 1300. www.onsemi.com figure 1. python 1300
noip1sn1300a www.onsemi.com 2 the devices are provided in a 48?pin lcc package and are available in monochrome, bayer color, and extended near?infrared (nir) configurations. ordering information part number description package python 1300 noip1sn1300a?qdi 1.3 megapixel, monochrome, lvds output 48?pin lcc noip1se1300a?qdi 1.3 megapixel, bayer color, lvds output noip1fn1300a?qdi 1.3 megapixel, monochrome with enhanced nir, lvds output noip2sn1300a?qdi 1.3 megapixel, monochrome, cmos (parallel) output noip2se1300a?qdi 1.3 megapixel, bayer color, cmos (parallel) output noip1sn1300a?qti 1.3 megapixel, monochrome, lvds output, protective foil noip1se1300a?qti 1.3 megapixel, bayer color, lvds output, protective foil noip1fn1300a?qti 1.3 megapixel, monochrome with enhanced nir, lvds output, protective foil noip3sn1300a?qdi 1.3 megapixel, 2 lvds outputs, monochrome noip3fn1300a?qdi 1.3 megapixel, 2 lvds outputs, nir enhanced monochrome noip3se1300a?qdi 1.3 megapixel, 2 lvds outputs, color noip3sn1300a?qti 1.3 megapixel, 2 lvds outputs, monochrome, protective foil noip3fn1300a?qti 1.3 megapixel, 2 lvds outputs, nir enhanced monochrome, protective foil noip3se1300a?qti 1.3 megapixel, 2 lvds outputs, color, protective foil python 500 noip1sn0500a?qdi 0.5 megapixel, monochrome, lvds output 48?pin lcc noip1se0500a?qdi 0.5 megapixel, bayer color, lvds output noip1fn0500a?qdi 0.5 megapixel, monochrome with enhanced nir, lvds output noip1sn0500a?qti 0.5 megapixel, monochrome, lvds output, protective foil noip1se0500a?qti 0.5 megapixel, bayer color, lvds output, protective foil noip1fn0500a?qti 0.5 megapixel, monochrome with enhanced nir, lvds output, protective foil python 300 noip1sn0300a?qdi 0.3 megapixel, monochrome, lvds output 48?pin lcc noip1se0300a?qdi 0.3 megapixel, bayer color, lvds output noip1fn0300a?qdi 0.3 megapixel, monochrome with enhanced nir, lvds output noip1sn0300a?qti 0.3 megapixel, monochrome, lvds output, protective foil noip1se0300a?qti 0.3 megapixel, bayer color, lvds output, protective foil noip1fn0300a?qti 0.3 megapixel, monochrome with enhanced nir, lvds output, protective foil the p1?sn/se/fn base part references the mono, color and nir enhanced versions of the 4 lvds interface; the p2?sn/se base part references the mono and color versions of the cmos interface; the p3?sn/se/fn base part references the mono, color and nir enhanced version of the 2 lvds interface. more details on the part number coding can be found at http://www .onsemi.com/pub_link/collateral/tnd310?d.pdf production package mark line 1: noip yxxrrrr a where y is either ?1? for 4 l vds outputs, ?2? for cmos parallel output, ?3? for 2 l vds outputs, where xx denotes mono micro lens (sn) or color micro lens (se) or nir micro lens (fn) rrrr is the resolution (1300), (0500) or (0300) line 2: ?qdi (without protective foil), ?qti (with protective foil) line 3: awlyyww where awl is production lot traceability, yyww is the 4?digit date code
noip1sn1300a www.onsemi.com 3 specifications key specifications table 1. general specifications parameter specification pixel type in?pixel cds. global shutter pixel architecture shutter type pipelined and triggered global shutter frame rate zero rot/ normal rot mode p1?sn/se/fn: python 300: 815/545 fps python 500: 545/385 fps python 1300: 210/165 fps p2?sn/se: 50/43 fps p3?sn/se/fn: na/90 fps master clock p1, p3?sn/se/fn: 72 mhz when pll is used, 360 mhz (10?bit) / 288 mhz (8?bit) when pll is not used p2?sn/se: 72 mhz windowing 8 randomly programmable windows. nor- mal, sub?sampled and binned readout modes adc resolution 10?bit, 8?bit (note 1) lvds outputs p1?sn/se/fn: 4/2/1 data + sync + clock p3?sn/se/fn: 2/1 data + sync + clock cmos outputs p2?sn/se: 10?bit parallel output, frame_valid, line_valid, clock data rate p1?sn/se/fn: 4 x 720 mbps (10?bit) / 4 x 576 mbps (8?bit) p2?sn/se: 72 mhz p3?sn/se/fn: 2 x 720 mbps (10?bit) power dissipation (10?bit mode) p1?sn/se/fn: 620 mw (4 data channels) p1, p3?sn/se/fn: 420 mw (2 data ch.) p1, p3?sn/se/fn: 270 mw (1 data ch.) p2?sn/se: 420 mw package type 48?pin lcc table 2. electro?optical specifications parameter specification active pixels python 300: 640 (h) x 480 (v) python 500: 800 (h) x 600 (v) python 1300: 1280 (h) x 1024 (v) pixel size 4.8 m x 4.8 m conversion gain 0.096 lsb10/e ? 140 v/e ? dark temporal noise < 9 e ? (normal rot, 1x gain) < 7 e ? (normal rot, 2x gain) responsivity at 550 nm 7.7 v/lux.s parasitic light sensitivity (pls) <1/8000 full well charge 10000 e ? quantum efficiency at 550 nm 56% pixel fpn < 1.0 lsb10 prnu < 2% or 10 lsb10 on half scale response of 525lsb10 mtf 68% @ 535 nm ? x?dir & y?dir psnl at 20 c 120 lsb10/s, 1200 e ? /s dark signal at 20 c 5 e ? /s, 0.5 lsb10/s dynamic range > 60 db in global shutter mode signal to noise ratio (snr max) 40 db table 3. recommended operating ratings (note 2) symbol description min max unit t j operating temperature range ?40 85 c functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. table 4. absolute maximum ratings (notes 3 and 4) symbol parameter min max unit abs (1.8 v supply group) abs rating for 1.8 v supply group ?0.5 2.2 v abs (3.3 v supply group) abs rating for 3.3 v supply group ?0.5 4.3 v t s abs storage temperature range ?40 +150 c abs storage humidity range at 85 c 85 %rh electrostatic discharge (esd) human body model (hbm): js?001?2010 2000 v charged device model (cdm): jesd22?c101 500 lu latch?up: jesd?78 100 ma stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. the adc is 11?bit, down?scaled to 10?bit. the python uses a larger word?length internally to provide 10?bit on the output. 2. operating ratings are conditions in which operation of the device is intended to be functional. 3. on semiconductor recommends that customers become familiar with, and follow the procedu res in jedec standard jesd625?a. refer to application note an52561. long term exposure toward the maximum storage temperature will accelerate color filter degradation . 4. caution needs to be taken to a void dried stains on the underside of the glass due to condensation. the glass lid glue is permeable and can absorb moisture if the sensor is placed in a high % rh environment.
noip1sn1300a www.onsemi.com 4 table 5. electrical specifications boldface limits apply for t j = t min to t max , all other limits t j = +30 c. (notes 5, 6, 7, 8 and 9) parameter description min typ max unit power supply parameters ? p1 ? sn/se/fn lvds (zrot) (note: all ground pins (gnd_18, gnd_33, gnd_colpc) should be connected to an external 0 v ground reference.) vdd_33 supply voltage, 3.3 v 3.2 3.3 3.4 v idd_33 current consumption 3.3 v supply 140 ma vdd_18 supply voltage, 1.8 v 1.7 1.8 1.9 v idd_18 current consumption 1.8 v supply 80 ma vdd_pix supply voltage, pixel 3.25 3.3 3.35 v idd_pix current consumption pixel supply 5 ma ptot total power consumption at vdd_33 = 3.3 v, vdd_18 = 1.8 v p1?sn/se/fn, 4 lvds, zrot 620 mw pstby_lp power consumption in low power standby mode 50 mw popt power consumption at lower pixel rates configurable power supply parameters ? p3 ? sn/se/fn lvds (nrot) (note: all ground pins (gnd_18, gnd_33, gnd_colpc) should be connected to an external 0 v ground reference.) vdd_33 supply voltage, 3.3 v 3.2 3.3 3.4 v idd_33 current consumption 3.3 v supply (2 / 1 lvds) 95 / 55 ma vdd_18 supply voltage, 1.8 v 1.7 1.8 1.9 v idd_18 current consumption 1.8 v supply (2 / 1 lvds) 55 / 45 ma vdd_pix supply voltage, pixel 3.25 3.3 3.35 v idd_pix current consumption pixel supply (2 / 1 lvds) 2 / 1 ma ptot total power consumption at vdd_33 = 3.3 v, vdd_18 = 1.8 v p3?sn/se/fn, 2 lvds, nrot p3?sn/se/fn, 1 lvds, nrot 420 270 mw pstby_lp power consumption in low power standby mode 50 mw popt power consumption at lower pixel rates configurable power supply parameters ? p2?sn/se cmos vdd_33 supply voltage, 3.3 v 3.2 3.3 3.4 v idd_33 current consumption 3.3 v supply 120 ma vdd_18 supply voltage, 1.8 v 1.7 1.8 1.9 v idd_18 current consumption 1.8 v supply 10 ma vdd_pix supply voltage, pixel 3.25 3.3 3.35 v idd_pix current consumption pixel supply 1 ma ptot total power consumption 420 mw pstby_lp power consumption in low power standby mode 50 mw popt power consumption at lower pixel rates configurable i/o ? p1?sn/se/fn, p3?sn/se/fn lvds (eia/tia?644): conforming to standard/additional specifications and deviations listed fserdata data rate on data channels ddr signaling ? 4 data channels, 1 synchronization channel 720 mbps product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 5. all parameters are characterized for dc conditions after thermal equilibrium is established. 6. this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. however, it is recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high impedance circuit. 7. minimum and maximum limits are guaranteed through test and design. 8. refer to acspython1300 available at the image sensor portal for detailed acceptance criteria specifications. 9. for power supply management recommendations, please refer to application note and9158.
noip1sn1300a www.onsemi.com 5 table 5. electrical specifications boldface limits apply for t j = t min to t max , all other limits t j = +30 c. (notes 5, 6, 7, 8 and 9) parameter unit max typ min description fserclock clock rate of output clock clock output for mesochronous signaling 360 mhz vicm lvds input common mode level 0.3 1.25 1.8 v tccsk channel to channel skew (training pattern allows per channel skew correction) 50 ps i/o ? p2?sn/se cmos (jedec? jesd8c?01): conforming to standard/additional specifications and deviations listed fpardata data rate on parallel channels (10?bit) 72 mbps cout output load (only capacitive load) 10 pf tr rise time (10% to 90% of input signal) 2.5 4.5 6.5 ns tf fall time (10% to 90% of input signal) 2 3.5 5 ns electrical interface ? p1 ? sn/se/fn lvds fin input clock rate when pll used 72 mhz fin input clock when lvds input used 360 mhz tidc input clock duty cycle when pll used 45 50 55 % tj input clock jitter 20 ps ratspi (= fin/fspi) 10?bit (4 lvds channels), pll used 6 10?bit (2 lvds channels), pll used 12 10?bit (1 lvds channel), pll used 24 10?bit (4 lvds channels), lvds input used 30 10?bit (2 lvds channels), lvds input used 60 10?bit (1 lvds channel), lvds input used 120 8?bit (4 lvds channels), pll used 6 8?bit (2 lvds channels), pll used 12 8?bit (1 lvds channel), pll used 24 8?bit (4 lvds channels), lvds input used 24 8?bit (2 lvds channels), lvds input used 48 8?bit (1 lvds channel), lvds input used 96 electrical interface ? p2?sn/se cmos fin input clock rate 72 mhz tidc input clock duty cycle 45 50 55 % tj input clock jitter 20 ps ratspi (= fin/fspi) 10?bit, pll bypassed 24 electrical interface ? p3 ? sn/se/fn lvds fin input clock rate when pll used 72 mhz fin input clock when lvds input used 360 mhz tidc input clock duty cycle when pll used 45 50 55 % tj input clock jitter 20 ps product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 5. all parameters are characterized for dc conditions after thermal equilibrium is established. 6. this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. however, it is recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high impedance circuit. 7. minimum and maximum limits are guaranteed through test and design. 8. refer to acspython1300 available at the image sensor portal for detailed acceptance criteria specifications. 9. for power supply management recommendations, please refer to application note and9158.
noip1sn1300a www.onsemi.com 6 table 5. electrical specifications boldface limits apply for t j = t min to t max , all other limits t j = +30 c. (notes 5, 6, 7, 8 and 9) parameter unit max typ min description ratspi (= fin/fspi) 10?bit (2 lvds channels), pll used 12 10?bit (1 lvds channel), pll used 24 10?bit (2 lvds channels), lvds input used 60 10?bit (1 lvds channel), lvds input used 120 frame specifications ? p1?sn/se/fn?lvds (zrot) maximum max units normal rot zero rot fps frame rate at full resolution 165 210 fps fps_roi1 xres x yres = 1024 x 1024 195 260 fps fps_roi2 xres x yres = 800 x 600 385 545 fps fps_roi3 xres x yres = 640 x 480 545 815 fps fps_roi4 xres x yres = 512 x 512 580 925 fps fps_roi5 xres x yres = 256 x 256 1400 2235 fps fpix pixel rate (4 channels at 72 mpix/s) 288 mpix/s frame specifications ? p2?sn/se cmos maximum units normal rot zero rot fps frame rate at full resolution 43 50 fps frame specifications ? p3?sn/se/fn lvds (nrot) maximum max units 2 lvds 1 lvds fps frame rate at full resolution 90 45 fps fps_roi1 xres x yres = 1024 x 1024 110 55 fps fps_roi2 xres x yres = 800 x 600 230 120 fps fps_roi3 xres x yres = 640 x 480 340 185 fps fps_roi4 xres x yres = 512 x 512 375 205 fps fps_roi5 xres x yres = 256 x 256 1110 660 fps fpix pixel rate (4 channels at 72 mpix/s) 144 mpix/s product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 5. all parameters are characterized for dc conditions after thermal equilibrium is established. 6. this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. however, it is recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high impedance circuit. 7. minimum and maximum limits are guaranteed through test and design. 8. refer to acspython1300 available at the image sensor portal for detailed acceptance criteria specifications. 9. for power supply management recommendations, please refer to application note and9158.
noip1sn1300a www.onsemi.com 7 color filter array the python color sensors are processed with a bayer rgb color pattern as shown in figure 2. pixel (0,0) has a red filter situated to the bottom left. figure 2. color filter array for the pixel array pixel (0;0) y x gb gr quantum efficiency figure 3. quantum efficiency curve for mono and color 0.0% 10.0% 20.0% 30.0% 40.0% 50.0% 60.0% 300 400 500 600 700 800 900 1000 1100 qe [%] wavelength [nm] red gr gb blue mono
noip1sn1300a www.onsemi.com 8 figure 4. quantum efficiency curve for standard and nir mono 0 10 20 30 40 50 60 70 300 400 500 600 700 800 900 1000 1100 qe [%] wavelengths [nm] mono nir
noip1sn1300a www.onsemi.com 9 ray angle and microlens array information an array of microlenses is placed over the cmos pixel array in order to improve the absolute responsivity of the photodiodes. the combined microlens array and pixel array has two important properties: 1. angular dependency of photoresponse of a pixel the photoresponse of a pixel with microlens in the center of the array to a fixed optical power with varied incidence angle is as plotted in figure 5, where definitions of angles x and y are as described by figure 6. 2. microlens shift across array and cra the microlens array is fabricated with a slightly smaller pitch than the array of photodiodes. this difference in pitch creates a varying degree of shift of a pixel?s microlens with regards to its photodiode. a shift in microlens position versus photodiode position will cause a tilted angle of peak photoresponse, here denoted chief ray angle (cra). microlenses and photodiodes are aligned with 0 shift and cra in the center of the array, while the shift and cra increases radially towards its edges, as illustrated by figure 7. the purpose of the shifted microlenses is to improve the uniformity of photoresponse when camera lenses with a finite exit pupil distance are used. the cra varies nearly linearly with distance from the center as illustrated in figure 8, with a corner cra of approximately 2.7 degrees. this edge cra is matching a lens with exit pupil distance of 80 mm. figure 5. central pixel photoresponse to a fixed optical power with incidence angle varied along x and y 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 ?30 ?20 ?10 0 10 20 30 normalized response [degrees deviation from normal] x = 0 y = 0 incidence angle x , y note that the photoresponse peaks near normal incidence for center pixels. figure 6. definition of angles used in figure 5.
noip1sn1300a www.onsemi.com 10 figure 7. principles of microlens shift shift center pixel (aligned) edge pixel (with shift) cra the center axes of the microlens and the photodiode coincide for the center pixels. for the edge pixels, there is a shift between the axes of the microlens and the photodiode causing a peak response incidence angle (cra) that deviates from the normal of the pixel array. figure 8. variation of peak responsivity angle (cra) as a function of distance from the center of the array 0 0.5 1 1.5 2 2.5 3 01234 diagonal x direction y direction cra [degrees] 1.7 2.1 2.7 distance from center [mm]
noip1sn1300a www.onsemi.com 11 overview figures 9 and 10 give an overview of the major functional blocks of the p1?sn/se/fn, p3?sn/se/fn and p2?sn/se sensor respectively. figure 9. block diagram ? p1?sn/se/fn, p3?sn/se/fn pixel array analog front end (afe) data formatting serializers & lvds interface lvds clock input 4, 2, 1 multiplexed lvds output channels 1 lvds sync channel 1 lvds clock channel 8 analog channels 8 x 10 bit digital channels 4 x 10 bit digital channels row dec od er column structure image core bias image core automatic exposure control (aec) clock distribution cmos clock input lvds receiver pll control & registers analog front end (afe) data formatting output mux cmos interface 8 analog channels 8 x 10 bit digital channels 10 bit parallel data frame valid indication line valid indication 4 x 10 bit digital channels row dec od er column structure image core bias image core pll figure 10. block diagram ? p2?sn/se cmos clock re set clock distribution cmos clock input automatic exposure control (aec) control & registers pixel array external trigger s spi interface re set external trigger s spi interface note: p3 part only has 2,1 multiplexed lvds output channels image core the image core consists of: ? pixel array ? address decoders and row drivers ? pixel biasing the python 1300 pixel array contains 1280 (h) x 1024 (v) readable pixels with a pixel pitch of 4.8 m. the python 300 and python 500 image arrays contain 672 (h) x 512 (v) and 832 (h) x 632 (v) readable pixels respectively, inclusive of 16 pixel rows and 16 pixel columns at every side to allow for reprocessing or color reconstruction. the sensors use in?pixel cds architecture, which makes it possible to achieve a low noise read out of the pixel array in global shutter mode with cds. the function of the row drivers is to access the image array line by line, or all lines together, to reset or read the pixel data. the row drivers are controlled by the on?chip sequencer and can access the pixel array. the pixel biasing block guarantees that the data on a pixel is transferred properly to the column multiplexer when the row drivers select a pixel line for readout. phase locked loop the pll accepts a (low speed) clock and generates the required high speed clock. optionally this pll can be bypassed. typical input clock frequency is 72 mhz. lvds clock receiver the lvds clock receiver receives an lvds clock signal and distributes the required clocks to the sensor. typical input clock frequency is 360 mhz in 10?bit mode and 288 mhz in 8?bit mode. the clock input needs to be terminated with a 100 resistor. column multiplexer all pixels of one image row are stored in the column sample?and?hold (s/h) stages. these stages store both the reset and integrated signal levels. the data stored in the column s/h stages is read out through 8 parallel differential outputs operating at a frequency of 36 mhz. at this stage, the reset signal and integrated signal values are transferred into an fpn?corrected differential signal. a programmable gain of 1x, 2x, or 4x can be applied to the signal. the column
noip1sn1300a www.onsemi.com 12 multiplexer also supports read?1?skip?1 and read?2?skip?2 mode. enabling this mode increases the frame rate, with a decrease in resolution. bias generator the bias generator generates all required reference voltages and bias currents used on chip. an external resistor of 47 k , connected between pin ibias_master and gnd_33, is required for the bias generator to operate properly. analog front end the afe contains 8 channels, each containing a pga and a 10?bit adc. for each of the 8 channels, a pipelined 10?bit adc is used to convert the analog image data into a digital signal, which is delivered to the data formatting block. a black calibration loop is implemented to ensure that the black level is mapped to match the correct adc input level. data formatting the data block receives data from two adcs and multiplexes this data to one data stream. a cyclic redundancy check (crc) code is calculated on the passing data. a frame synchronization data block transmits synchronization codes such as frame start, line start, frame end, and line end indications. the data block calculates a crc once per line for every channel. this crc code can be used for error detection at the receiving end. serializer and lvds interface (p1?sn/se/fn, p3?sn/se/fn only) the serializer and lvds interface block receives the formatted (10?bit or 8?bit) data from the data formatting block. this data is serialized and transmitted by the lvds 288 mhz output driver. in 10?bit mode, the maximum output data rate is 720 mbps per channel. in 8?bit mode, the maximum output data rate is 576 mbps per channel. in addition to the lvds data outputs, two extra lvds outputs are available. one of these outputs carries the output clock, which is skew aligned to the output data channels. the second lvds output contains frame format synchronization codes to serve system?level image reconstruction. output mux (p2?sn/se) the output mux multiplexes the four data channels to one channel and transmits the data words using a 10?bit parallel cmos interface. frame synchronization information is communicated by means of frame and line valid strobes. channel multiplexer the p1?sn/se/fn lvds channel multiplexer provides a 4:2 and 4:1 feature, in addition to utilizing all 4 output channels. the p3? sn/se/fn lvds cha nnel multiplexer provides a 2:1 feature, in addition to utilizing both the output channels. sequencer the sequencer: ? controls the image core. starts and stops integration and control pixel readout. ? operates the sensor in master or slave mode. ? applies the window settings. organizes readouts so that only the configured windows are read. ? controls the column multiplexer and analog core. applies gain settings and subsampling modes at the correct time, without corrupting image data. ? starts up the sensor correctly when leaving standby mode. automatic exposure control the aec block implements a control system to modulate the exposure of an image. both integration time and gains are controlled by this block to target a predefined illumination level.
noip1sn1300a www.onsemi.com 13 operating modes global shutter mode the python 300, python 500, and python 1300 operate in pipelined or triggered global shuttering modes. in this mode, light integration, light integration takes place on all pixels in parallel, although subsequent readout is sequential. figure 11 shows the integration and readout sequence for the global shutter. all pixels are light sensitive at the same period of time. the whole pixel core is reset simultaneously and after the integration time all pixel values are sampled together on the storage node inside each pixel. the pixel core is read out line by line after integration. note that the integration and readout can occur in parallel or sequentially. the integration starts at a certain period, relative to the frame start. figure 11. global shutter operation pipelined global shutter mode in pipelined global shutter mode, the integration and readout are done in parallel. images are continuously read and integration of frame n is ongoing during readout of the previous frame n?1. the readout of every frame starts with a frame overhead time (fot), during which the analog value on the pixel diode is transferred to the pixel memory element. after the fot, the sensor is read out line per line and the readout of each line is preceded by the row overhead time (rot). figure 12 shows the exposure and readout time line in pipelined global shutter mode. master mode the python 300, python 500, and python 1300 operate in pipelined or triggered global shuttering modes. in this mode, light, the integration time is set through the register interface and the sensor integrates and reads out the images autonomously. the sensor acquires images without any user interaction. figure 12. integration and readout for pipelined shutter reset n exposure time n reset n+1 exposure time n+1 readout frame n-1 fot fot readout frame n rot line readout fot fot slave mode the slave mode adds more manual control to the sensor. the integration time registers are ignored in this mode and the integration time is instead controlled by an external pin. as soon as the control pin is asserted, the pixel array goes out of reset and integration starts. the integration continues until the user or system deasserts the external pin. upon a falling edge of the trigger input, the image is sampled and the readout begins. figure 13 shows the relation between the external trigger signal and the exposure/readout timing.
noip1sn1300a www.onsemi.com 14 figure 13. pipelined shutter operated in slave mode reset n exposure time n reset n+1 exposure t im e n+1 readout n?1 fot fot readout n triggered global shutter mode in this mode, manual intervention is required to control both the integration time and the start of readout. after the integration time, indicated by a user controlled pin, the image core is read out. after this sequence, the sensor goes to an idle mode until a new user action is detected. the three main differences with the pipelined global shutter mode are: ? upon user action, one single image is read. ? normally, integration and readout are done sequentially. however, the user can control the sensor in such a way that two consecutive batches are overlapping, that is, having concurrent integration and readout. ? integration and readout is under user control through an external pin. this mode requires manual intervention for every frame. the pixel array is kept in reset state until requested. the triggered global mode can also be controlled in a master or in a slave mode. master mode in this mode, a rising edge on the synchronization pin is used to trigger the start of integration and readout. the integration time is defined by a register setting. the sensor autonomously integrates during this predefined time, after which the fot starts and the image array is readout sequentially. a falling edge on the synchronization pin does not have any impact on the readout or integration and subsequent frames are started again for each rising edge. figure 14 shows the relation between the external trigger signal and the exposure/readout timing. if a rising edge is applied on the external trigger before the exposure time and fot of the previous frame is complete, it is ignored by the sensor. figure 14. triggered shutter operated in master mode reset n exposure time n reset n+1 exposure time n+1 readout n-1 fot fot readout n rot line readout external trigger no effect on falling edge register controlled fot fot slave mode integration time control is identical to the pipelined shutter slave mode. an external synchronization pin controls the start of integration. when it is de?asserted, the fot starts. the analog value on the pixel diode is transferred to the pixel memory element and the image readout can start. a request for a new frame is started when the synchronization pin is asserted again.
noip1sn1300a www.onsemi.com 15 normal and zero row overhead time (rot) modes in pipelined global shutter mode, the integration and readout are done in parallel. images are continuously read out and integration of frame n is ongoing during readout of the previous frame n?1. the readout of every frame starts with a frame overhead time (fot), during which the analog value of the pixel diode is transferred to the pixel memory element. after the fot, the sensor is read out line by line and the readout of each line is preceded by a row overhead time (rot) as shown in figure 15. in reduced/zero rot operation mode (refer to figure 16), the row blanking and kernel readout occur in parallel. this mode is called reduced rot as a part of the rot is done while the image row is readout. the actual rot can thus be longer, however the perceived rot will be shorter (?overhead? spent per line is reduced). the integration time and gain parameters can be reconfigured without any visible image artifact in normal rot mode. column?level of fset corrections are required in zero rot mode. refer to column?level image correction application note in the python developer?s guide and9362/d available at the image sensor portal . this operation mode can be used for two reasons: ? reduced total line time. ? lower power due of reduced clock?rate. note: zero rot is not supported on p3?sn/se/fn devices. figure 15. integration and rea dout sequence of the sensor operating in pipelined global shutter mode with normal rot readout. rot ys rot ys+1 rot ye readout ye valid data fot () readout ys readout ys figure 16. integration and rea dout sequence of the sensor operating in pipelined global shutter mode with zero rot readout. rot ys (blanked out ) rot readout ys+1 ys rot readout ye ye?1 rot readout dummy ye valid data fot ()
noip1sn1300a www.onsemi.com 16 sensor operation flowchart figure 17 shows the sensor operation flowchart. the sensor has six different ?states?. every state is indicated with the oval circle. these states are power off, low power standby, standby (1), standby (2), idle, running. figure 17. sensor operation flowchart power up sequence enable clock management - part 2 (first pass after hard reset) low-power standby required register upload standby (2) soft power-up idle enable sequencer running sensor (re-)configuration (optional) disable sequencer soft power-down disable clock management part 2 power off power down sequence intermediate standby enable clock management - part 2 (not first pass after hard reset) sensor (re-)configuration (optional) sensor (re-)configuration (optional) assertion of reset_n pin enable clock management - part 1 poll lock indication (only when pll is enabled) disable clock management part 1 standby (1)
noip1sn1300a www.onsemi.com 17 sensor states low power standby in low power standby state, all power supplies are on, but internally every block is disabled. no internal clock is running (pll / lvds clock receiver is disabled). all register settings are unchanged. only a subset of the spi registers is active for read/write in order to be able to configure clock settings and leave the low power standby state. the only spi registers that should be touched are the ones required for the ?enable clock management? action described in enable clock management ? part 1 on page 18 standby (1) in standby state, the pll/lvds clock receiver is running, but the derived logic clock signal is not enabled. standby (2) in standby state, the derived logic clock signal is running. all spi registers are active, meaning that all spi registers can be accessed for read or write operations. all other blocks are disabled. idle in the idle state, all internal blocks are enabled, except the sequencer block. the sensor is ready to start grabbing images as soon as the sequencer block is enabled. running in running state, the sensor is enabled and grabbing images. the sensor can be operated in global master/slave modes. user actions: power up functional mode sequences power up sequence figure 18 shows the power up sequence of the sensor. the figure indicates that the first supply to ramp?up is the vdd_18 supply, followed by vdd_33 and vdd_pix respectively. it is important to comply with the described sequence. any other supply ramping sequence may lead to high current peaks and, as consequence, a failure of the sensor power up. the clock input should start running when all supplies are stabilized. when the clock frequency is stable, the reset_n signal can be de?asserted. after a wait period of 10 s, the power up sequence is finished and the first spi upload can be initiated. note: the ?clock input? can be the cmos pll clock input (clk_pll), or the lvds clock input (lvds_clock_inn/p) in case the pll is bypassed. figure 18. power up sequence reset_n vdd_18 vdd_33 clock input vdd_pix > 10us > 10us > 10us > 10us spi upload > 10us enable clock management ? part 1 the ?enable clock management? action configures the clock management blocks and activates the clock generation and distribution circuits in a pre?defined way. first, a set of clock settings must be uploaded through the spi register. these settings are dependent on the desired operation mode of the sensor. table 6 shows the spi uploads to be executed to configure the sensor for p1?sn/se/fn, p3?sn/se/fn 10?bit serial mode, with the pll, and all available lvds channels. note that the spi uploads to be executed to configure the sensor for other supported modes (p1?sn/se/fn 8?bit serial, p2?sn/se 10?bit parallel, ...) are available to customers under nda at the on semiconductor image sensor portal . in the serial modes, if the pll is not used, the l vds clock input must be running. in the p2?sn/se 10?bit parallel mode, the pll is bypassed. the clk_pll clock is used as sensor clock. it is important to follow the upload sequence listed in table 6.
noip1sn1300a www.onsemi.com 18 use of phase locked loop if pll is used, the pll is started after the upload of the spi registers. the pll requires (dependent on the settings) some time to generate a stable output clock. a lock detect circuit detects if the clock is stable. when complete, this is flagged in a status register. note: the lock detect status must not be checked for the p2?sn/se sensor. check the pll_lock flag 24[0] by reading the spi register. when the flag is set, the ?enable clock management? part 2? action can be continued. when pll is not used, this step can be bypassed as shown in figure 17 on page 16. table 6. enable clock management register upload: part 1 upload # address data description p1?sn/se/fn, p3?sn/se/fn 10?bit mode with pll 1 2 0x0000 monochrome sensor 0x0001 color sensor 2 8 0x0000 release pll soft reset 3 16 0x0003 enable pll 4 17 0x2113 configure pll 5 20 0x0000 configure clock management 6 26 0x2280 configure pll lock detector 7 27 0x3d2d configure pll lock detector 8 32 0x7004 configure clock management for p1 only 0x6014 configure clock management for p3 only p2?sn/se 10?bit mode 1 2 0x0002 monochrome sensor 0x0003 color sensor 2 16 0x0007 enable pll bypass mode 3 20 0x0000 configure clock management 4 32 0x700c configure clock management enable clock management ? part 2 the next step to configure the clock management consists of spi uploads which enables all internal clock distribution. the required uploads are listed in table 4. note that it is important to follow the upload sequence listed in table 7. table 7. enable clock management register upload: part 2 upload # address data description p1?sn/se/fn, p3?sn/se/fn 10?bit mode with pll 1 9 0x0000 release clock generator soft reset 2 32 0x7006 enable logic clock for p1 only 0x6016 enable logic clock for p3 only 3 34 0x0001 enable logic blocks p2?sn/se 10?bit mode 1 9 0x0000 release clock generator soft reset 2 32 0x700e enable logic clock 3 34 0x0001 enable logic blocks
noip1sn1300a www.onsemi.com 19 required register upload in this phase, the ?reserved? register settings are uploaded through the spi register. different settings are not allowed and may cause the sensor to malfunction. the required uploads are listed in table 8. table 8. required register upload upload # address p1?sn/se/fn 10?bit mode with pll (4 lvds zrot) address p2?sn/se 10?bit mode (zrot) address p3?sn/se/fn 10?bit mode with pll (2 lvds nrot) 1 41 0x085f 41 0x085f 41 0x085f 2 42 0x4100 42 0x4100 42 0x4100 3 43 0x0008 43 0x0008 43 0x0008 4 65 0x382b 65 0x382b 65 0x382b 5 66 0x53c8 66 0x53c8 66 0x53c4 6 67 0x0665 67 0x0344 67 0x0645 7 68 0x0085 68 0x0085 68 0x0085 8 69 0x0088 69 0x0088 69 0x0048 9 70 0x1111 70 0x1111 70 0x1111 10 72 0x0010 72 0x0010 72 0x0017 11 128 0x4714 128 0x4714 128 0x4714 12 129 0x8001 129 0xa001 129 0x8001 13 171 0x1002 130 0x0001 171 0x1002 14 175 0x0080 171 0x1002 175 0x0080 15 176 0x00e6 175 0x0080 176 0x00e6 16 177 0x0400 176 0x00e6 177 0x0400 17 192 0x080c 177 0x0400 192 0x0800 18 194 0x0224 192 0x080c 194 0x0224 19 197 0x0306 194 0x0224 197 0x0306 20 204 0x01e1 197 0x0103 204 0x01e3 21 207 0x0000 204 0x01e1 207 0x0000 22 211 0x0e49 207 0x0000 211 0x0e39 23 215 0x111f 211 0x0e49 215 0x111f 24 216 0x7f00 215 0x111f 216 0x7f00 25 219 0x0020 216 0x7f00 219 0x0020 26 220 0x3a28 219 0x0017 220 0x3728 27 221 0x624d 220 0x2c1c 221 0x6245 28 222 0x624d 221 0x623c 222 0x6230 29 224 0x3e5e 222 0x623c 224 0x3e5e 30 227 0x0000 224 0x3e02 227 0x0000 31 250 0x2081 227 0x0000 250 0x2081 32 384 0xc800 250 0x2081 384 0xc800 33 385 0xfb1f 384 0xc800 385 0xfb1f 34 386 0xfb1f 385 0xfb1f 386 0xfb1f 35 387 0xfb12 386 0xfb17 387 0xfb12 36 388 0xf903 387 0xf802 388 0xf903 37 389 0xf802 388 0xf003 389 0xf802 38 390 0xf30f 389 0xf30f 390 0xf30f
noip1sn1300a www.onsemi.com 20 table 8. required register upload upload # p3?sn/se/fn 10?bit mode with pll (2 lvds nrot) address p2?sn/se 10?bit mode (zrot) address p1?sn/se/fn 10?bit mode with pll (4 lvds zrot) address 39 391 0xf30f 390 0xf30f 391 0xf30f 40 392 0xf30f 391 0xf30f 392 0xf30f 41 393 0xf30a 392 0xf101 393 0xf30a 42 394 0xf101 393 0xf005 394 0xf101 43 395 0xf00a 394 0xf247 395 0xf00a 44 396 0xf24b 395 0xf226 396 0xf24b 45 397 0xf226 396 0xf002 397 0xf226 46 398 0xf001 397 0xf402 398 0xf001 47 399 0xf402 398 0xf001 399 0xf402 48 400 0xf001 399 0xf20f 400 0xf001 49 401 0xf402 400 0xf20f 401 0xf402 50 402 0xf001 401 0xf205 402 0xf001 51 403 0xf401 402 0xf002 403 0xf401 52 404 0xf007 403 0xc801 404 0xf007 53 405 0xf20f 404 0xcc01 405 0xf20f 54 406 0xf20f 405 0xc802 406 0xf20f 55 407 0xf202 406 0xc800 407 0xf202 56 408 0xf006 407 0xc800 408 0xf006 57 409 0xec02 408 0xc801 409 0xec02 58 410 0xe801 409 0xcc04 410 0xe801 59 411 0xec02 410 0xc801 411 0xec02 60 412 0xe801 411 0xc800 412 0xe801 61 413 0xec02 412 0x0030 413 0xec02 62 414 0xc801 413 0x0078 414 0xc801 63 415 0xc800 414 0x0072 415 0xc800 64 416 0xc800 415 0x1071 416 0xc800 65 417 0xcc02 416 0x3073 417 0xcc02 66 418 0xc801 417 0x1073 418 0xc801 67 419 0xcc02 418 0x0072 419 0xcc02 68 420 0xc801 419 0x0031 420 0xc801 69 421 0xcc02 420 0x00b1 421 0xcc02 70 422 0xc805 421 0x01b8 422 0xc805 71 423 0xc800 422 0x00b2 423 0xc800 72 424 0x0030 423 0x10b1 424 0x0030 73 425 0x207c 424 0x30b3 425 0x2073 74 426 0x2071 425 0x10b3 426 0x2071 75 427 0x0074 426 0x00b2 427 0x0071 76 428 0x107f 427 0x0030 428 0x1079 77 429 0x1072 428 0x0030 429 0x1072 78 430 0x1074 429 0x0178 430 0x0073
noip1sn1300a www.onsemi.com 21 table 8. required register upload upload # p3?sn/se/fn 10?bit mode with pll (2 lvds nrot) address p2?sn/se 10?bit mode (zrot) address p1?sn/se/fn 10?bit mode with pll (4 lvds zrot) address 79 431 0x0076 430 0x0072 431 0x0031 80 432 0x0031 431 0x1071 432 0x21b6 81 433 0x21bb 432 0x3073 433 0x20b1 82 434 0x20b1 433 0x1073 434 0x00b1 83 435 0x20b1 434 0x0072 435 0x10b9 84 436 0x00b1 435 0x0031 436 0x10b2 85 437 0x10bf 436 0x00b1 437 0x00b1 86 438 0x10b2 437 0x00b8 438 0x0030 87 439 0x10b4 438 0x00b2 439 0x0030 88 440 0x00b1 439 0x10b1 440 0x2176 89 441 0x0030 440 0x30b3 441 0x2071 90 442 0x0030 441 0x10b3 442 0x2071 91 443 0x217b 442 0x00b2 443 0x0071 92 444 0x2071 443 0x0030 444 0x1079 93 445 0x2071 445 0x1072 94 446 0x0074 446 0x0073 95 447 0x107f 447 0x0031 96 448 0x1072 448 0x20b3 97 449 0x1074 449 0x00b1 98 450 0x0076 450 0x10b9 99 451 0x0031 451 0x10b2 100 452 0x20bb 452 0x00b1 101 453 0x20b1 453 0x0030 102 454 0x20b1 103 455 0x00b1 104 456 0x10bf 105 457 0x10b2 106 458 0x10b4 107 459 0x00b1 108 460 0x0030 note: register uploads for other supported operation modes can be accessed at the image sensor portal on myon.
noip1sn1300a www.onsemi.com 22 soft power up during the soft power up action, the internal blocks are enabled and prepared to start processing the image data stream. this action exists of a set of spi uploads. the soft power up uploads are listed in table 9. table 9. soft power up register upload upload # address data description p1?sn/se/fn, p3?sn/se/fn 10?bit mode with pll (p1 in zrot, p3 in nrot) 1 10 0x0000 release soft reset state 2 32 0x7007 enable analog clock for p1 0x6017 enable analog clock for p3 3 40 0x0003 enable column multiplexer 4 42 0x4103 configure image core 5 48 0x0001 enable afe 6 64 0x0001 enable biasing block 7 72 0x0017 enable charge pump 8 112 0x0007 enable lvds transmitters p2?sn/se 10?bit mode (zrot) 1 10 0x0000 release soft reset state 2 32 0x700f enable analog clock 3 40 0x0003 enable column multiplexer 4 42 0x4103 configure image core 5 48 0x0001 enable afe 6 64 0x0001 enable biasing block 7 72 0x0017 enable charge pump
noip1sn1300a www.onsemi.com 23 enable sequencer during the ?enable sequencer? action, the frame grabbing sequencer is enabled. the sensor starts grabbing images in the configured operation mode. refer to sensor states on page 17. the ?enable sequencer ? action consists of a set of register uploads. the required uploads are listed in table 10. table 10. enable sequencer register upload upload # address data description 1 192 0x080d enable sequencer for p1 in zrot 0x0801 enable sequencer for p3 in nrot user actions: functional modes to power down sequences disable sequencer during the ?disable sequencer? action, the frame grabbing sequencer is stopped. the sensor stops grabbing images and returns to the idle mode. the ?disable sequencer? action consists of a set of register uploads. as listed in table 11. table 11. disable sequencer register upload upload # address data description 1 192 0x080c disable sequencer for p1 in zrot 0x0800 disable sequencer for p3 in nrot soft power down during the soft power down action, the internal blocks are disabled and the sensor is put in standby state to reduce the current dissipation. this action exists of a set of spi uploads. the soft power down uploads are listed in table 12. table 12. soft power down register upload upload # address data description p1?sn/se/fn, p3?sn/se/fn 10?bit mode with pll (p1 in zrot, p3 in nrot) 1 10 0x0999 soft reset 2 32 0x7006 disable analog clock for p1 0x6016 disable analog clock for p3 3 40 0x0000 disable column multiplexer 4 42 0x4100 image core config 5 48 0x0000 disable afe 6 64 0x0000 disable biasing block 7 72 0x0010 disable charge pump 8 112 0x0000 disable lvds transmitters p2?sn/se 10?bit mode (zrot) 1 10 0x0999 soft reset 2 32 0x700e disable analog clock 3 40 0x0000 disable column multiplexer 4 42 0x4100 image core config 5 48 0x0000 disable afe 6 64 0x0000 disable biasing block 7 72 0x0010 disable charge pump
noip1sn1300a www.onsemi.com 24 disable clock management ? part 2 the ?disable clock management? action stops the internal clocking to further decrease the power dissipation. this action can be implemented with the spi uploads as shown in table 13. table 13. disable clock management register upload: part 2 upload # address data description p1?sn/se/fn, p3?sn/se/fn 10?bit mode with pll 1 9 0x0000 soft reset clock generator 2 32 0x7004 disable logic clock for p1 0x6014 disable logic clock for p3 3 34 0x0000 disable logic blocks p2?sn/se 10?bit mode 1 9 0x0000 soft reset clock generator 2 32 0x700c disable logic clock 3 34 0x0000 disable logic blocks disable clock management ? part 1 the ?disable clock management? action stops the internal clocking to further decrease the power dissipation. this action can be implemented with the spi uploads as shown in table 14. table 14. disable clock management register upload: part 1 upload # address data description p1?sn/se/fn, p3?sn/se/fn 10?bit mode with pll 1 8 0x0099 soft reset pll 2 16 0x0000 disable pll power down sequence figure 19 illustrates the timing diagram of the preferred power down sequence. it is important that the sensor is in reset before the clock input stops running. otherwise, the internal pll becomes unstable and the sensor gets into an unknown state. this can cause high peak currents. the same applies for the ramp down of the power supplies. the preferred order to ramp down the supplies is first vdd_pix, second vdd_33, and finally vdd_18. any other sequence can cause high peak currents. note: the ?clock input? can be the cmos pll clock input (clk_pll), or the lvds clock input (lvds_clock_inn/p) in case the pll is bypassed. figure 19. power down sequence reset_n vdd_18 vdd_33 clock input vdd_pix > 10us > 10us > 10us > 10us
noip1sn1300a www.onsemi.com 25 sensor reconfiguration during the standby, idle, or running state several sensor parameters can be reconfigured. ? frame rate and exposure time: frame rate and exposure time changes can occur during standby, idle, and running states by modifying registers 199 to 203. refer to page 30?32 for more information. ? signal path gain: signal path gain changes can occur during standby, idle, and running states by modifying registers 204/205. refer to page 37 for more information. ? windowing: changes with respect to windowing can occur during standby, idle, and running states. refer to multiple window readout on page 32 for more information. ? subsampling: changes of the subsampling mode can occur during standby, idle, and running states by modifying register 192. refer to subsampling on page 33 for more information. ? shutter mode: the shutter mode can only be changed during standby or idle mode by modifying register 192. reconfiguring the shutter mode during running state is not supported. sensor configuration this device contains multiple configuration registers. some of these registers can only be configured while the sensor is not acquiring images (while register 192[0] = 0), while others can be configured while the sensor is acquiring images. for the latter category of registers, it is possible to distinguish the register set that can cause corrupted images (limited number of images containing visible artifacts) from the set of registers that are not causing corrupted images. these three categories are described here. static readout parameters some registers are only modified when the sensor is not acquiring images. reconfiguration of these registers while images are acquired can cause corrupted frames or even interrupt the image acquisition. therefore, it is recommended to modify these static configurations while the sequencer is disabled (register 192[0] = 0). the registers shown in t able 15 should not be reconfigured during image acquisition. a specific configuration sequence applies for these registers. refer to the operation flow and startup description. table 15. static readout parameters group addresses description clock generator 32 configure according to recommendation image core 40 configure according to recommendation afe 48 configure according to recommendation bias 64?71 configure according to recommendation lvds 112 configure according to recommendation sequencer mode selection 192 [6:1] operation modes are: ? triggered_mode ? slave_mode all reserved registers keep reserved registers to their default state, unless otherwise described in the recommendation dynamic configuration potentially causing image artifacts the category of registers as shown in table 16 consists of configurations that do not interrupt the image acquisition process, but may lead to one or more corrupted images during and after the reconfiguration. a corrupted image is an image containing visible artifacts. a typical example of a corrupted image is an image which is not uniformly exposed. the effect is transient in nature and the new configuration is applied after the transient effect. table 16. dynamic configuration potentially causing image artifacts group addresses description black level configuration 128?129 197[12:8] reconfiguration of these registers may have an impact on the black?level calibration algorithm. the effect is a transient number of images with incorrect black level com- pensation. sync codes 129[13] 116?126 incorrect sync codes may be generated during the frame in which these registers are modified. datablock test configurations 144, 146?150 modification of these registers may generate incorrect test patterns during a transient frame.
noip1sn1300a www.onsemi.com 26 dynamic readout parameters it is possible to reconfigure the sensor while it is acquiring images. frame related parameters are internally resynchronized to frame boundaries, such that the modified parameter does not affect a frame that has already started. however, there can be restrictions to some registers as shown in table 17. some reconfiguration may lead to one frame being blanked. this happens when the modification requires more than one frame to settle. the image is blanked out and training patterns are transmitted on the data and sync channels. table 17. dynamic readout parameters group addresses description subsampling/binning 192[7] 192[8] subsampling or binning is synchronized to a new frame start. roi configuration 195 256?303 a roi switch is only detected when a new window is selected as the active window (reconfiguration of register 195). reconfiguration of the roi dimension of the active window does not lead to a frame blank and can cause a corrupted image. exposure reconfiguration 199?203 exposure reconfiguration does not cause artifact. however, a latency of one frame is observed unless reg_seq_exposure_sync_mode is set to ?1? in triggered global mode (master). gain reconfiguration 204 gains are synchronized at the start of a new frame. optionally, one frame latency can be incorporated to align the gain updates to the exposure updates (refer to register 204[13] ? gain_lat_comp). freezing active configurations though the readout parameters are synchronized to frame boundaries, an update of multiple registers can still lead to a transient effect in the subsequent images, as some configurations require multiple register uploads. for example, to reconfigure the exposure time in master global mode, both the fr_length and exposure registers need to be updated. internally, the sensor synchronizes these configurations to frame boundaries, but it is still possible that the reconfiguration of multiple registers spans over two or even more frames. to avoid inconsistent combinations, freeze the active settings while altering the spi registers by disabling synchronization for the corresponding functionality before reconfiguration. when all registers are uploaded, re?enable the synchronization. the sensor?s sequencer then updates its active set of registers and uses them for the coming frames. the freezing of the active set of registers can be programmed in the sync_configuration registers, which can be found at the spi address 206. figure 20 shows a reconfiguration that does not use the sync_configuration option. as depicted, new spi configurations are synchronized to frame boundaries. figure 21 shows the usage of the sync_configuration settings. before uploading a set of registers, the corresponding sync_configuration is de?asserted. after the upload is completed, the sync_configuration is asserted again and the sensor resynchronizes its set of registers to the coming frame boundaries. as seen in the figure, this ensures that the uploads performed at the end of frame n+2 and the start of frame n+3 become active in the same frame (frame n+4). figure 20. frame synchronization of configurations (no freezing) frame nframe n+1?frame n+2?frame n+3 frame n+4 time line spi registers active registers figure 21. reconfiguration using sync_configuration frame nframe n+1?frame n+2?frame n+3?frame n+4 time line sync_configuration spi registers active registers this configuration is not taken into account as sync_register is inactive. note: spi updates are not taken into account while sync_configuration is inactive. the active configuration is frozen for the sensor. table 18 lists the several sync_configuration possibilities along with the respective registers being frozen.
noip1sn1300a www.onsemi.com 27 table 18. alternate sync configurations group affected registers description sync_black_lines black_lines update of black line configuration is not synchronized at start of frame when ?0?. the sensor continues with its previous configurations. sync_exposure mult_timer fr_length exposure update of exposure configurations is not synchronized at start of frame when ?0?. the sensor continues with its previous configurations. sync_gain mux_gainsw afe_gain update of gain configurations is not synchronized at start of frame when ?0?. the sensor continues with its previous configurations. sync_roi roi_active0[7:0] subsampling binning update of active roi configurations is not synchronized at start of frame when ?0?. the sensor continues with its previous configurations. note: the window configurations themselves are not frozen. reconfiguration of active windows is not gated by this setting. window configuration global shutter mode up to 8 windows can be defined in global shutter mode (pipelined or triggered). the windows are defined by registers 256 to 303. each window can be activated or deactivated separately using register 195. it is possible to reconfigure the inactive windows while the sensor is acquiring images. switching between predefined windows is achieved by activation of the respective windows. this way a minimum number of registers need to be uploaded when it is necessary to switch between two or more sets of windows. as an example of this, scanning the scene at higher frame rates using multiple windows and switching to full frame capture when the object is tracked. switching between the two modes only requires an upload of one register. black calibration the sensor automatically calibrates the black level for each frame. therefore, the device generates a configurable number of electrical black lines at the start of each frame. the desired black level in the resulting output interface can be configured and is not necessarily targeted to ?0?. configuring the target to a higher level yields some information on the left side of the black level distribution, while the other end of the distribution tail is clipped to ?0? when setting the black level target to ?0?. the black level is calibrated for the 8 columns contained in one kernel. this implies 8 black level of fsets are generated and applied to the corresponding columns. configurable parameters for the black?level algorithm are listed in table 19. table 19. configurable parameters for black level algorithm address register name description black line generation 197[7:0] black_lines this register configures the number of black lines that are generated at the start of a frame. at least one black line must be generated. the maximum number is 255. note: when the automatic black?level calibration algorithm is enabled, make sure that this register is configured properly to produce sufficient black pixels for the black?level filtering. the number of black pixels generated per line is dependent on the operation mode and window configu- rations: each black line contains 162 kernels. 197[12:8] gate_first_line a number of black lines are blanked out when a value different from 0 is configured. these blanked out lines are not used for black calibration. it is recommended to enable this functionality, because the first line can have a different behavior caused by boundary effects. when enabling, the number of black lines must be set to at least two in order to have valid black samples for the calibration algorithm. black value filtering 129[0] auto_blackcal_enable internal black?level calibration functionality is enabled when set to ?1?. required black level offset com- pensation is calculated on the black samples and applied to all image pixels. when set to ?0?, the automatic black?level calibration functionality is disabled. it is possible to apply an offset compensation to the image pixels, which is defined by the registers 129[10:1]. note: black sample pixels are not compensated; the raw data is sent out to provide external statistics and, optionally, calibrations. 129[9:1] blackcal_offset black calibration offset that is added or subtracted to each regular pixel value when auto_blackcal_en- able is set to ?0?. the sign of the offset is determined by register 129[10] (blackcal_offset_dec). note: all channels use the same offset compensation when automatic black calibration is disabled. 129[10] blackcal_offset_dec sign of blackcal_offset. if set to ?0?, the black calibration offset is added to each pixel. if set to ?1?, the black calibration offset is subtracted from each pixel. this register is not used when auto_blackcal_enable is set to ?1?.
noip1sn1300a www.onsemi.com 28 table 19. configurable parameters for black level algorithm address description register name black line generation 128[10:8] black_samples the black samples are low?pass filtered before being used for black level calculation. the more sam- ples are taken into account, the more accurate the calibration, but more samples require more black lines, which in turn affects the frame rate. the effective number of samples taken into account for filtering is 2^ black_samples. note: an error is reported by the device if more samples than available are requested (refer to register 136). black level filtering monitoring 136 blackcal_error0 an error is reported by the device if there are requests for more samples than are available (each bit corresponding to one data path). the black level is not compensated correctly if one of the channels indicates an error. there are three possible methods to overcome this situation and to perform a correct offset compensation: ? increase the number of black lines such that enough samples are generated at the cost of increas- ing frame time (refer to register 197). ? relax the black calibration filtering at the cost of less accurate black level determination (refer to register 128). ? disable automatic black level calibration and provide the offset via spi register upload. note that the black level can drift in function of the temperature. it is thus recommended to perform the offset calibration periodically to avoid this drift. note: the maximum number of samples taken into account for black level statistics is half the number of kernels.
noip1sn1300a www.onsemi.com 29 serial peripheral interface the sensor configuration registers are accessed through an spi. the spi consists of four wires: ? sck: serial clock ? ss_n: active low slave select ? mosi: master out, slave in, or serial data in ? miso: master in, slave out, or serial data out the spi is synchronous to the clock provided by the master (sck) and asynchronous to the sensor?s system clock. when the master wants to write or read a sensor?s register, it selects the chip by pulling down the slave select line (ss_n). when selected, data is sent serially and synchronous to the spi clock (sck). figure 22 shows the communication protocol for read and write accesses of the spi registers. the python 300, python 500, and python 1300 image sensors use 9?bit addresses and 16?bit data words. data driven by the system is colored blue in figure 16, while data driven by the sensor is colored yellow. the data in grey indicates high?z periods on the miso interface. red markers indicate sampling points for the sensor (mosi sampling); green markers indicate sampling points for the system (miso sampling during read operations). the access sequence is: 3. select the sensor for read or write by pulling down the ss_n line. 4. one spi clock cycle after selecting the sensor, the 9?bit data is transferred, most significant bit first. the sck clock is passed through to the sensor as indicated in figure 22. the sensor samples this data on a rising edge of the sck clock (mosi needs to be driven by the system on the falling edge of the sck clock). 5. the tenth bit sent by the master indicates the type of transfer: high for a write command, low for a read command. 6. data transmission: - for write commands, the master continues sending the 16?bit data, most significant bit first. - for read commands, the sensor returns the requested address on the miso pin, most significant bit first. the miso pin must be sampled by the system on the falling edge of sck (assuming nominal system clock frequency and maximum 10 mhz spi frequency). 7. when data transmission is complete, the system deselects the sensor one clock period after the last bit transmission by pulling ss_n high. note that the maximum frequency for the spi interface scales with the input clock frequency, bit depth and lvds output multiplexing as described in table 5. consecutive spi commands can be issued by leaving at least two spi clock periods between two register uploads. deselect the chip between the spi uploads by pulling the ss_n pin high. figure 22. spi read and write timing diagram .. a1 a0 `1' a8 d15 d14 .. .. .. .. d1 d0 sck mosi ss_n miso a7 .. .. .. a1 a0 `0' a8 sck mosi ss_n miso a7 .. .. d15 d14 .. .. .. .. d1 d0 ts_mosi th_mosi t_sssck t_sckss ts _miso th_miso t_sckss t_sssck ts _mos i th_mosi tsck tsck spi ? write spi ? read
noip1sn1300a www.onsemi.com 30 table 20. spi timing requirements group addresses description units tsck sck clock period 100 (*) ns tsssck ss_n low to sck rising edge tsck ns tsckss sck falling edge to ss_n high tsck ns ts_mosi required setup time for mosi 20 ns th_mosi required hold time for mosi 20 ns ts_miso setup time for miso tsck/2?10 ns th_miso hold time for miso tsck/2?20 ns tspi minimal time between two consecutive spi accesses (not shown in figure) 2 x tsck ns *value indicated is for nominal operation. the maximum spi clock frequency depends on the sensor configuration (operation mode, input clock). tsck is defined as 1/f spi . see text for more information on spi clock frequency restrictions. image sensor timing and readout the following sections describe the configurations for single slope reset mechanism. dual and triple slope handling during global shutter operation is similar to the single slope operation. extra integration time registers are available. global shutter mode pipelined global shutter (master) the integration time is controlled by the registers fr_length[15:0] and exposure[15:0]. the mult_timer configuration defines the granularity of the registers reset_length and exposure. it is read as number of system clock cycles (14.706 ns nominal at 68 mhz) for the p1?sn/se/fn, p3?sn/se/fn version and 18 mhz cycles (55.556 ns nominal) for the p2?sn/se version. the exposure control for (pipelined) global master mode is depicted in figure 23. the pixel values are transferred to the storage node during fot, after which all photo diodes are reset. the reset state remains active for a certain time, defined by the reset_length and mult_timer registers, as shown in the figure. note that meanwhile the image array is read out line by line. after this reset period, the global photodiode reset condition is abandoned. this indicates the start of the integration or exposure time. the length of the exposure time is defined by the registers exposure and mult_timer. note: the start of the exposure time is synchronized to the start of a new line (during rot) if the exposure period starts during a frame readout. as a consequence, the effective time during which the image core is in a reset state is extended to the start of a new line. ? make sure that the sum of the reset time and exposure time exceeds the time required to readout all lines. if this is not the case, the exposure time is extended until all (active) lines are read out. ? alternatively, it is possible to specify the frame time and exposure time. the sensor automatically calculates the required reset time. this mode is enabled by the fr_mode register. the frame time is specified in the register fr_length. figure 23. integration control for (pipelined) global shutter mode (master) reset integrating reset integrating image array global reset readout fot fot fot fot fot fot reset_length x mult_timer frame n frame n+1 exposure state = rot = readout = readout dummy line (blanked) exposure x mult_timer
noip1sn1300a www.onsemi.com 31 triggered global shutter (master) in master triggered global mode, the start of integration time is controlled by a rising edge on the trigger0 pin. the exposure or integration time is defined by the registers exposure and mult_timer, as in the master pipelined global mode. the fr_length configuration is not used. this operation is graphically shown in figure 24. figure 24. exposure time control in triggered shutter mode (master) reset integrating reset integrating image array global reset readout fot fot fot fot fot fot exposure x mult_timer frame n frame n+1 exposure state (no effect on falling edge) trigger0 = rot = readout = readout dummy line (blanked) notes: ? the falling edge on the trigger pin does not have any impact. note however the trigger must be asserted for at least 100 ns. ? the start of the exposure time is synchronized to the start of a new line (during rot) if the exposure period starts during a frame readout. as a consequence, the effective time during which the image core is in a reset state is extended to the start of a new line. ? if the exposure timer expires before the end of readout, the exposure time is extended until the end of the last active line. ? the trigger pin needs to be kept low during the fot. the monitor pins can be used as a feedback to the fpga/controller (eg. use monitor0, indicating the very first line when monitor_select = 0x5 ? a new trigger can be initiated after a rising edge on monitor0). triggered global shutter (slave) exposure or integration time is fully controlled by means of the trigger pin in slave mode. the registers fr_length, exposure and mult_timer are ignored by the sensor. a rising edge on the trigger pin indicates the start of the exposure time, while a falling edge initiates the transfer to the pixel storage node and readout of the image array. in other words, the high time of the trigger pin indicates the integration time, the period of the trigger pin indicates the frame time. the use of the trigger during slave mode is shown in figure 25. notes: ? the registers exposure, fr_length, and mult_timer are not used in this mode. ? the start of exposure time is synchronized to the start of a new line (during rot) if the exposure period starts during a frame readout. as a consequence, the effective time during which the image core is in a reset state is extended to the start of a new line. ? if the trigger is de?asserted before the end of readout, the exposure time is extended until the end of the last active line. ? the trigger pin needs to be kept low during the fot. the monitor pins can be used as a feedback to the fpga/controller (eg. use monitor0, indicating the very first line when monitor_select = 0x5 ? a new trigger can be initiated after a rising edge on monitor0). figure 25. exposure time control in global?slave mode reset integrating reset integrating image array global reset readout fot fot fot fot fot fot frame n frame n+1 exposure state trigger0 = rot = readout = readout dummy line (blanked)
noip1sn1300a www.onsemi.com 32 additional features multiple window readout the python 300, python 500, and python 1300 image sensors support multiple window readout, which means that only the user?selected regions of interest (roi) are read out. this allows limiting data output for every frame, which in turn allows increasing the frame rate. in global shutter mode, up to eight rois can be configured. window configuration figure 26 shows the four parameters defining a region of interest (roi). figure 26. region of interest configuration y-start y-end x-start?x-end roi 0 ? x?start[7:0] x?start defines the x?starting point of the desired window. the sensor reads out 8 pixels in one single clock cycle. as a consequence, the granularity for configuring the x?start position is also 8 pixels for no sub sampling. the value configured in the x?start register is multiplied by 8 to find the corresponding column in the pixel array. ? x?end[7:0] this register defines the window end point on the x?axis. similar to x?start, the granularity for this configuration is one kernel. x?end needs to be larger than x?start. ? y?start[9:0] the starting line of the readout window. the granularity of this setting is one line, except with color sensors where it needs to be an even number. ? y?end[9:0] the end line of the readout window. y?end must be configured larger than y?start. this setting has the same granularity as the y?start configuration. up to eight windows can be defined, possibly (partially) overlapping, as illustrated in figure 27. figure 27. overlapping multiple window configuration y0_start y1_start y0_end y1_end x0_start x1_start x0_end x1_end roi 0 roi 1 the sequencer analyses each line that need to be read out for multiple windows. restrictions the following restrictions for each line are assumed for the user configuration: ? windows are ordered from left to right, based on their x?start address: x_start_roi(i) x_start_roi(j) and x_end_roi(i) x_end_roi(j) where j i > processing multiple windows the sequencer control block houses two sets of counters to construct the image frame. as previously described, the y?counter indicates the line that needs to be read out and is incremented at the end of each line. for the start of the frame, it is initialized to the y?start address of the first window and it runs until the y?end address of the last window to be read out. the last window is configured by the configuration registers and it is not necessarily window #7. the x?counter starts counting from the x?start address of the window with the lowest id which is active on the addressed line. only windows for which the current y?address is enclosed are taken into account for scanning. other windows are skipped.
noip1sn1300a www.onsemi.com 33 figure 28 illustrates a practical example of a configuration with five windows. the current position of the read pointer (ys) is indicated by a red line crossing the image array. for this position of the read pointer, three windows need to be read out. the initial start position for the x?kernel pointer is the x?start configuration of roi1. kernels are scanned up to the roi3 x?end position. from there, the x?pointer jumps to the next window, which is roi4 in this illustration. when reaching roi4?s x?end position, the read pointer is incremented to the next line and xs is reinitialized to the starting position of roi1. notes: ? the starting point for the readout pointer at the start of a frame is the y?start position of the first active window. ? the read pointer is not necessarily incremented by one, but depending on the configuration, it can jump in y?direction. in figure 28, this is the case when reaching the end of roi0 where the read pointer jumps to the y?start position of roi1 ? the x?pointer starting position is equal to the x?start configuration of the first active window on the current line addressed. this window is not necessarily window #0. ? the x?pointer is not necessarily incremented by one each cycle. at the end of a window it can jump to the start of the next window. ? each window can be activated separately. there is no restriction on which window and how many of the 8 windows are active. figure 28. scanning the image array with five windows roi 0 roi 1 roi 4 ys roi 3 roi 2 subsampling subsampling is used to reduce the image resolution. this allows increasing the frame rate. two subsampling modes are supported: for monochrome and nir enhanced sensors (p1?sn/fn, p2?sn and p3?sn/fn) and color sensors (p1?se / p2?se / p3?se). monochrome and nir sensors these sensors utilize the read?1?skip?1 subsampling scheme. subsampling occurs both in x? and y? direction. color sensors for color sensors, the read?2?skip?2 subsampling scheme is used. subsampling occurs both in x? and y? direction. figure 29 shows which pixels are read and which ones are skipped. figure 29. subsampling scheme for monochrome and color sensors
noip1sn1300a www.onsemi.com 34 binning pixel binning is a technique in which different pixels belonging to a rectangular bin are averaged in the analog domain. two?by?two pixel binning is available with the monochrome and nir enhanced image sensors (p1?sn/fn, p2?sn, p3?sn/fn). this implies that two adjacent pixels are averaged both in column and row. binning is configurable using a register setting. pixel binning is not supported on python color option (p1?se / p2?se / p3?se) and in zero rot mode. notes: 1. register 194[13:12] needs to be configured to 0x0 for 2x2 pixel binning and to 0x1 for 2x1 binning. binning occurs only in x direction. 2. binning in y-direction cannot be used in combination with pipelined integration and readout. the integration time and readout time should be separated in time (do not coincide). reverse readout in y?direction reverse readout in y?direction can be done by toggling reverse_y (reg 194[8]). the reference for y_start and y_end pointers is reversed. multiple slope integration ?multiple slope integration? is a method to increase the dynamic range of the sensor. the python 300, python 500, and python 1300 support up to three slopes. figure 30 shows the sensor response to light when the sensor is used with one slope, two slopes, and three slopes. the x?axis represents the light power; the y?axis shows the sensor output signal. the kneepoint of the multiple slope curves are adjustable in both position and voltage level. it is clear that when using only one slope (red curve), the sensor has the same responsivity over the entire range, until the output saturates at the point indicated with ?single slope saturation point?. to increase the dynamic range of the sensor, a second slope is applied in the dual slope mode (green curve). the sensor has the same responsivity in the black as for a single slope, but from ?knee point 1? on, the sensor is less responsive to incoming light. the result is that the saturation point is at a higher light power level. to further increase the dynamic range, a third slope can be applied, resulting in a second knee point. the multiple slope function is only available in global shutter modes. refer to section global shutter mode on page 30 for general notes applicable to the global shutter operation and more particular to the use of the trigger0 pin. figure 30. multiple slope operation slope 1?slope 2 slope 3 light output 1023 0 `kneepoint 1' `kneepoint 2' single slope saturation point dual slope saturation point triple slope saturation point
noip1sn1300a www.onsemi.com 35 kneepoint configuration (multiple slope reset levels) the kneepoint reset levels are configured by means of dac configurations in the image core. the dual slope kneepoint is configured with the dac_ds configuration, while the triple slope kneepoint is configured with the dac_ts register setting. both are located on address 41. multiple slope integration in ?master mode? (pipelined or triggered) in master mode, the time stamps for the double and triple slope resets are configured in a similar way as the exposure time. they are enabled through the registers dual_slope_enable and triple_slope_enable and their values are defined by the registers exposure_ds and exposure_ts . note: dual and triple slope sequences must start after readout of the previous frame is fully completed. figure 31 shows the frame timing for pipelined master mode with dual and triple slope integration and fr_mode = ?0? (fr_length representing the reset length). in triggered master mode, the start of integration is initiated by a rising edge on trigger0 , while the falling edge does not have any relevance. exposure duration and dual/triple slope points are defined by the registers. figure 31. multiple slope operation in master mode for fr_mode = ?0? (pipelined) slave mode in slave mode, the register settings for integration control are ignored. the user has full control through the trigger0, trigger1 and trigger2 pins. a falling edge on trigger1 initiates the dual slope reset while a falling edge on trigger2 initiates the triple slope reset sequence. rising edges on trigger1 and trigger2 do not have any impact. note: dual and triple slope sequences must start after readout of the previous frame is fully completed. figure 32. multiple slope operation in slave mode
noip1sn1300a www.onsemi.com 36 black reference the sensor reads out one or more black lines at the start of every new frame. the number of black lines to be generated is programmable and is minimal equal to 1. the length of the black lines depends on the operation mode. the sensor always reads out the entire line (160 kernels), independent of window configurations. the black references are used to perform black calibration and offset compensation in the data channels. the raw black pixel data is transmitted over the usual output interface, while the regular image data is compensated (can be bypassed). on the output interface, black lines can be seen as a separate window, however without frame start and ends (only line start/end). the sync code following the line start and line end indications (?window id?) contains the active window number, which is 0. black reference data is classified by a bl code. signal path gain analog gain stages referring to table 21, three gain settings are available in the analog data path to apply gain to the analog signal before it is digitized. the gain amplifier can apply a gain of approximately 1x to 4x to the analog signal. the moment a gain reconfiguration is applied and becomes valid can be controlled by the gain_lat_comp configuration. with ?gain_lat_comp? set to ?0?, the new gain configurations are applied from the very next frame. with ?gain_lat_comp? set to ?1?, the new gain settings are postponed by one extra frame. this feature is useful when exposure time and gain are reconfigured together, as an exposure time update always has one frame latency. table 21. signal path gain stages address gain setting gain stage 1 (204[4:0]) gain stage 2 (204[12:5]) overall gain normal rot zero rot normal rot zero rot normal rot zero rot 204[12:0] 0x01e3 1 na 1 na 1 na 204[12:0] 0x01e1 1.9 1 1 1 1.9 1 204[12:0] 0x01e4 3.5 1.8 1 1 3.5 1.8 204[12:0] 0x01e8 14 8 1 1 14 8 note: the sensor performance specifications are tested at unity gain. analog gain above 2x affects noise performance. all other gain settings shown in this table are tested for sensor functionality. digital gain stage the digital gain stage allows fine gain adjustments on the digitized samples. the gain configuration is an absolute 5.7 unsigned number (5 digits before and 7 digits after the decimal point).
noip1sn1300a www.onsemi.com 37 automatic exposure control the exposure control mechanism has the shape of a general feedback control system. figure 33 shows the high level block diagram of the exposure control loop. figure 33. automatic exposure control loop aec statistics aec filter aec enforcer requested ga in changes total gain integration time analog gain (coarse steps) requested illumination level (target) digital gain (fine steps) image capture three main blocks can be distinguished: ? the statistics block compares the average of the current image?s samples to the configured target value for the average illumination of all pixels ? the relative gain change request from the statistics block is filtered through the aec filter block in the time domain (low pass filter) before being integrated. the output of the filter is the total requested gain in the complete signal path. ? the enforcer block accepts the total requested gain and distributes this gain over the integration time and gain stages (both analog and digital) the automatic exposure control loop is enabled by asserting the aec_enable configuration in register 160. note: dual and triple slope integration is not supported in conjunction with the aec. aec statistics block the statistics block calculates the average illumination of the current image. based on the difference between the calculated illumination and the target illumination the statistics block requests a relative gain change. statistics subsampling and windowing for average calculation, the statistics block will sub?sample the current image or windows by taking every fourth sample into account. note that only the pixels read out through the active windows are visible for the aec. in the case where multiple windows are active, the samples will be selected from the total samples. samples contained in a region covered by multiple (overlapping) window will be taking into account only once. it is possible to define an aec specific sub?window on which the aec will calculate it?s average. for instance, the sensor can be configured to read out a larger frame, while the illumination is measured on a smaller region of interest, e.g. center weighted as shown in table 22. table 22. aec sample selection register name description 192[10] roi_aec_enable when 0x0, all active windows are selected for statistics calculation. when 0x1, the aec samples are selected from the active pixels contained in the region of interest defined by roi_aec 253?255 roi_aec these registers define a window from which the aec samples will be selected when roi_aec_enable is asserted. configuration is similar to the regular region of interests. the intersection of this window with the active windows define the selected pixels. it is important that this window at least overlaps with one or more active windows.
noip1sn1300a www.onsemi.com 38 target illumination the target illumination value is configured by means of register desired_intensity as shown in table 23. table 23. aec target illumination configuration register name description 161[9:0] desired_in- tensity target intensity value, on 10?bit scale. for 8?bit mode, target value is con- figured on desired_intensity[9:2] color sensor the weight of each color can be configured for color sensors by means of scale factors. note these scale factor are only used to calculate the statistics in order to compensate for (off?chip) white balancing and/or color matrices. the pixel values itself are not modified. the scale factors are configured as 3.7 unsigned numbers (0x80 = unity). refer to t able 24 for color scale factors. for mono sensors, configure these factors to their default value. table 24. color scale factors register name description 162[9:0] red_scale_factor red scale factor for aec statistics 163[9:0] green1_scale_fa ctor green1 scale factor for aec statistics 164[9:0] green2_scale_fa ctor green2 scale factor for aec statistics 165[9:0] blue_scale_factor blue scale factor for aec statistics aec filter block the filter block low?pass filters the gain change requests received from the statistics block. the filter can be restarted by asserting the restart_filter configuration of register 160. aec enforcer block the enforcer block calculates the four different gain parameters, based on the required total gain, thereby respecting a specific hierarchy in those configurations. some (digital) hysteresis is added so that the (analog) sensor settings don?t need to change too often. exposure control parameters the several gain parameters are described below, in the order in which these are controlled by the aec for large adjustments. small adjustments are regulated by digital gain only. ? exposure time the exposure is the time between the global image array reset de?assertion and the pixel charge transfer. the granularity of the integration time steps is configured by the mult_timer register. note: the exposure_time register is ignored when the aec is enabled. the register fr_length defines the frame time and needs to be configured accordingly. ? analog gain the sensor has two analog gain stages, configurable independently from each other. t ypically the aec shall only regulate the first stage. ? digital gain the last gain stage is a gain applied on the digitized samples. the digital gain is represented by a 5.7 unsigned number (i.e. 7 bits after the decimal point). while the analog gain steps are coarse, the digital gain stage makes it possible to achieve very fine adjustments.
noip1sn1300a www.onsemi.com 39 aec control range the control range for each of the exposure parameters can be pre?programmed in the sensor. t able 25 lists the relevant registers. table 25. minimum and maximum exposure control parameters register name description 168[15:0] min_exposure lower bound for the integration time applied by the aec 169[1:0] min_mux_gain lower bound for the first stage analog amplifier. this stage has three configurations with the following approximative gains: 0x0 = 1x 0x1 = 2x 0x2 = 4x 169[3:2] min_afe_gain lower bound for the second stage analog amplifier. this stage has one configuration with the following approximative gain: 0x0 = 1.00x 169[15:4] min_digital_gain lower bound for the digital gain stage. this configuration specifies the effective gain in 5.7 unsigned format 170[15:0] max_exposure upper bound for the integration time applied by the aec 171[1:0] max_mux_gain upper bound for the first stage analog amplifier. this stage has three configurations with the following approximative gains: 0x0 = 1x 0x1 = 2x 0x2 = 4x 171[3:2] max_afe_gain upper bound for the second stage analog amplifier this stage has one configuration with the following approximative gain: 0x0 = 1.00x 171[15:4] max_digit- al_gain upper bound for the digital gain stage. this configuration specifies the effective gain in 5.7 unsigned format aec update frequency as an integration time update has a latency of one frame, the exposure control parameters are evaluated and updated every other frame. note: the gain update latency must be postpone to match the integration time latency. this is done by asserting the gain_lat_comp register on address 204[13]. exposure control status registers configured integration and gain parameters are reported to the user by means of status registers. the sensor provides two levels of reporting: the status registers reported in the aec address space are updated once the parameters are recalculated and requested to the internal sequencer. the status registers residing in the sequencer?s address space on the other hand are updated once these parameters are taking effect on the image readout. refer to table 26 reflecting the aec and sequencer status registers. table 26. exposure control status registers register name description aec status registers 184[15:0] total_pixels total number of pixels taken into account for the aec statistics. 186[9:0] average calculated average illumination level for the current frame. 187[15:0] exposure aec calculated exposure. note: this parameter is updated at the frame end. 188[1:0] mux_gain aec calculated analog gain (1 st stage) note: this parameter is updated at the frame end. 188[3:2] afe_gain aec calculated analog gain (2 st stage) note: this parameter is updated at the frame end. 188[15:4] digital_gain aec calculated digital gain (5.7 unsigned format) note: this parameter is updated at the frame end.
noip1sn1300a www.onsemi.com 40 table 26. exposure control status registers register name description sequencer status registers 242[15:0] mult_timer mult_timer for current frame (global shutter only). note: this parameter is updated once it takes effect on the image. 243[15:0] reset_length image array reset length for the current frame (global shutter only). note: this parameter is updated once it takes effect on the image. 244[15:0] exposure exposure for the current frame. note: this parameter is updated once it takes effect on the image. 245[15:0] exposure_ds dual slope exposure for the current frame. note this parameter is not controlled by the aec. note: this parameter is updated once it takes effect on the image. 246[15:0] exposure_ts triple slope exposure for the current frame. note this parameter is not controlled by the aec. note: this parameter is updated once it takes effect on the image. 247[4:0] mux_gainsw 1 st stage analog gain for the current frame. note: this parameter is updated once it takes effect on the image. register name description 247[12:5] afe_gain 2 st stage analog gain for the current frame. note: this parameter is updated once it takes effect on the image. 248[11:0] db_gain digital gain configuration for the current frame (5.7 unsigned format). note: this parameter is updated once it takes effect on the image. 248[12] dual_slope dual slope configuration for the current frame note 1 : this parameter is updated once it takes effect on the image. note 2 : this parameter is not controlled by the aec. 248[13] triple_slope triple slope configuration for the current frame. note 1 : this parameter is updated once it takes effect on the image. note 2 : this parameter is not controlled by the aec.
noip1sn1300a www.onsemi.com 41 mode changes and frame blanking dynamically reconfiguring the sensor may lead to corrupted or non-uniformilly exposed frames. for some reconfigurations, the sensor automatically blanks out the image data during one frame. frame blanking is summarized in the following table for the sensor?s image related modes. note: major mode switching (i.e. switching between master, triggered or slave mode) must be performed while the sequencer is disabled (reg_seq_enable = 0x0). table 27. dynamic sensor reconfiguration and frame blanking configuration corrupted frame blanked out frame notes shutter mode and operation triggered_mode do not reconfigure while the sensor is acquiring images. disable image acquisition by setting reg_seq_enable = 0x0. slave_mode do not reconfigure while the sensor is acquiring images. disable image acquisition by setting reg_seq_enable = 0x0. subsampling enabling: no disabling: yes configurable configurable with blank_subsampling_ss register. binning no configurable configurable with blank_subsampling_ss register frame timing black_lines no no exposure control mult_timer no no latency is 1 frame fr_length no no latency is 1 frame exposure no no latency is 1 frame gain mux_gainsw no no latency configurable by means of gain_lat_comp register afe_gain no no latency configurable by means of gain_lat_comp register. db_gain no no latency configurable by means of gain_lat_comp register. window/roi roi_active see note no windows containing lines previously not read out may lead to corrupted frames. roi*_configuration* see note no reconfiguring the windows by means of roi*_configuration* may lead to corrupted frames when configured close to frame boundaries. it is recommended to (re)configure an inactive window and switch the roi_active register. see notes on roi_active. black calibration black_samples no no if configured within range of configured black lines auto_blackal_enable see note no manual correction factors become instantly active when auto_blackcal_enable is deasserted during operation. blackcal_offset see note no manual blackcal_offset updates are instantly active. crc calculation crc_seed no no impacts the transmitted crc sync channel bl_0 no no impacts the sync channel information, not the data channels. img_0 no no impacts the sync channel information, not the data channels. crc_0 no no impacts the sync channel information, not the data channels. tr_0 no no impacts the sync channel information, not the data channels.
noip1sn1300a www.onsemi.com 42 temperature sensor the python 300, python 500, and python 1300 image sensors have an on?chip temperature sensor which returns a digital code (tsensor) of the silicon junction temperature. the tsensor output is a 8?bit digital count between 0 and 255, proportional to the temperature of the silicon substrate. this reading can be translated directly to a temperature reading in c by calibrating the 8?bit readout at 0 c and 85 c to achieve an output accuracy of 2 c. the tsensor output can also be calibrated using a single temperature point (example: room temperature or the ambient temperature of the application), to achieve an output accuracy of 5 c. note that any process variation will result in an offset in the bit count and that offset will remain within 5 c over the temperature range of 0 c and 85 c. tsensor output digital code can be read out through the spi interface. output of the temperature sensor to the spi: tempd_reg_temp<7:0>: this is the 8?bit n count readout proportional to temperature. input from the spi: the reg_tempd_enable is a global enable and this enables or disables the temperature sensor when logic high or logic low respectively. the temperature sensor is reset or disabled when the input reg_tempd_enable is set to a digital low state. calibration using one temperature point the temperature sensor resolution is fixed for a given type of package for the operating range of 0 c to +85 c and hence devices can be calibrated at any ambient temperature of the application, with the device configured in the mode of operation. interpreting the actual temperature for the digital code readout: the formula used is t j = r (nread ? ncalib) + tcalib t j = junction die temperature r = resolution in degrees/lsb (typical 0.75 deg/lsb) nread = tsensor output (lsb count between 0 and 255) tcalib = tsensor calibration temperature ncalib = tsensor output reading at tcalib monitor pins the internal sequencer has two monitor outputs (pin 44 and pin 45) that can be used to communicate the internal states from the sequencer. a three?bit register configures the assignment of the pins as shown in table 28. table 28. register setting for the monitor select pin monitor_select [2:0] 192 [13:11] monitor pin description 0x0 monitor0 monitor1 ?0? ?0? 0x1 monitor0 monitor1 integration time rot indication (?1? during rot, ?0? outside) 0x2 monitor0 monitor1 integration time dual/triple slope integration (asserted during ds/ts fot sequence) 0x3 monitor0 monitor1 start of x?readout indication black line indication (?1? during black lines, ?0? outside) 0x4 monitor0 monitor1 frame start indication start of rot indication 0x5 monitor0 monitor1 first line indication (?1? during first line, ?0? for all others) start of rot indication 0x6 monitor0 monitor1 rot indication (?1? during rot, ?0? outside) start of x?readout indication 0x7 monitor0 monitor1 start of x?readout indication for black lines start of x?readout indication for image lines
noip1sn1300a www.onsemi.com 43 data output format the python 300, python 500, and python 1300 image sensors are available in two lvds output configuration, p1 and p3. the p1 configuration utilizes four lvds output channels together with an lvds clock output and an lvds synchronization output channel. the p3 configuration consists of two lvds output channels together with an lvds clock output and an lvds synchronization output channel. the python 1300 is also available in a cmos output configuration ? p2, which includes a 10?bit parallel cmos output together with a cmos clock output and ?frame valid? and ?line valid? cmos output signals. p1?sn/se/fn, p3?sn/se/fn: lvds interface version lvds output channels the image data output occurs through four lvds data channels where a synchronization lvds channel and an lvds output clock signal synchronizes the data. referring to table 21, the four data channels on the p1 option are used to output the image data only, while on the p3 option, two data channel channels are utilized. the sync channel transmits information about the data sent over these data channels (includes codes indicating black pixels, normal pixels, and crc codes). 8?bit / 10?bit mode the sensor can be used in 8?bit or 10?bit mode. in 10?bit mode, the words on data and sync channel have a 10?bit length. the output data rate is 720 mbps. in 8?bit mode, the words on data and sync channel have an 8?bit length, the output data rate is 576 mbps. note that the 8?bit mode can only be used to limit the data rate at the consequence of image data word depth. it is not supported to operate the sensor in 8?bit mode at a higher clock frequency to achieve higher frame rates. the p1 option supports 10?bit/8?bit in zrot/nrot mode, while the p3 option supports 10?bit nrot mode only. frame format the frame format in 8?bit mode is identical to the 10?bit mode with the exception that the sync and data word depth is reduced to eight bits. the frame format in 10?bit mode is explained by example of the readout of two (overlapping) windows as shown in figure 34(a). the readout of a frame occurs on a line?by?line basis. the read pointer goes from left to right, bottom to top. figure 34 indicates that, after the fot is completed, the sensor reads out a number of black lines for black calibration purposes. after these black lines, the windows are processed. first a number of lines which only includes information of ?roi 0? are sent out, starting at position y0_start. when the line at position y1_start is reached, a number of lines containing data of ?roi 0? and ?roi 1? are sent out, until the line position of y0_end is reached. from there on, only data of ?roi 1? appears on the data output channels until line position y1_end is reached during read out of the image data over the data channels, the sync channel sends out frame synchronization codes which give information related to the image data that is sent over the four data output channels. each line of a window starts with a line start (ls) indication and ends with a line end (le) indication. the line start of the first line is replaced by a frame start (fs); the line end of the last line is replaced with a frame end indication (fe). each such frame synchronization code is followed by a window id (range 0 to 7). for overlapping windows, the line synchronization codes of the overlapping windows with lower ids are not sent out (as shown in the illustration: no le/fe is transmitted for the overlapping part of window 0). note: in figure 34, only frame start and frame end sync words are indicated in (b). crc codes are also omitted from the figure. for additional information on the synchronization codes, please refer to application note and5001.
noip1sn1300a www.onsemi.com 44 figure 34. p1?sn/se/fn, p3?sn/se/fn: frame sync codes (a) (b) y0_start y1_start y0_end y1_end x0_start x1_start x0_end x1_end roi 0 reset n exposure time n reset n+1 exposure time n+1 roi 0 fot fot integration time handling readout handling fot roi 1 readout frame n-1 readout frame n roi 0 roi 1 fs0 fs1 fe1 fs0 fs1 fe1 figure 35 shows the detail of a black line readout during global or full?frame readout. figure 35. p1?sn/se/fn, p3?sn/se/fn: time line for black line readout data channels sync channel data channels sync channel sequencer internal state line ys line ys+1 line ye black timeslot 0 training tr ls bl le training tr fot rot rot rot rot crc bl bl bl bl bl timeslot 1 timeslot 157 timeslot 158 timeslot 159 crc timeslot
noip1sn1300a www.onsemi.com 45 figure 36 shows shows the details of the readout of a number of lines for single window readout, at the beginning of the frame. figure 36. p1?sn/se/fn, p3?sn/se/fn: time line for single window readout (at the start of a frame) data channels sync channel data channels sync channel sequencer internal state line ys line ys+1 line ye black timeslot xstart training tr fs id img le training tr fot rot rot rot id rot crc img img img img img timeslot xstart + 1 timeslot xend - 2 timeslot xend - 1 timeslot xend crc timeslot figure 37 shows the detail of the readout of a number of lines for readout of two overlapping windows. figure 37. p1?sn/se/fn, p3?sn/se/fn: time line showing the readout of two overlapping windows data channels sync channel data channels sync channel sequencer internal state line ys+1 line ye black timeslot xstartm training tr ls idm img le training tr fot rot rot rot idn rot crc img ls idn img img timeslot xstartn timeslot xendn line ys img frame synchronization for 10?bit mode table 29 sh ows the structure of the frame synchronization code. note that the table shows the default data word (configurable) for 10?bit mode. if more than one window is active at the same time, the sync channel transmits the frame synchronization codes of the window with highest index only. table 29. frame synchronization code details for 10?bit mode sync word bit position register address default value description 9:7 n/a 0x5 frame start indication 9:7 n/a 0x6 frame end indication 9:7 n/a 0x1 line start indication 9:7 n/a 0x2 line end indication 6:0 117[6:0] 0x2a these bits indicate that the received sync word is a frame synchronization code. the value is programmable by a register setting
noip1sn1300a www.onsemi.com 46 ? window identification frame synchronization codes are always followed by a 3?bit window identification (bits 2:0). this is an integer number, ranging from 0 to 7, indicating the active window. if more than one window is active for the current cycle, the highest window id is transmitted. ? data classification codes for the remaining cycles, the sync channel indicates the type of data sent through the data links: black pixel data (bl), image data (img), or training pattern (tr). these codes are programmable by a register setting. the default values are listed in table 30. table 30. synchronization channel default identification code values for 10?bit mode sync word bit position register address default value description 9:0 118 [9:0] 0x015 black pixel data (bl). this data is not part of the image. the black pixel data is used internally to correct channel offsets. 9:0 119 [9:0] 0x035 valid pixel data (img). the data on the data output channels is valid pixel data (part of the image). 9:0 125 [9:0] 0x059 crc value. the data on the data output channels is the crc code of the finished image data line. 9:0 126 [9:0] 0x3a6 training pattern (tr). the sync channel sends out the training pattern which can be programmed by a register setting. frame synchronization in 8?bit mode the frame synchronization words are configured using the same registers as in 10?bit mode. the two least significant bits of these configuration registers are ignored and not sent out. table 32 shows the structure of the frame synchronization code, together with the default value, as specified in spi registers. the same restriction for overlapping windows applies in 8?bit mode. table 31. frame synchronization code details for 8?bit mode sync word bit position register address default value description 7:5 n/a 0x5 frame start (fs) indication 7:5 n/a 0x6 frame end (fe) indication 7:5 n/a 0x1 line start (ls) indication 7:5 n/a 0x2 line end (le) indication 4:0 117 [6:2] 0x0a these bits indicate that the received sync word is a frame synchronization code. the value is programmable by a register setting. ? window identification similar to 10?bit operation mode, the frame synchronization codes are followed by a window identification. the window id is located in bits 4:2 (all other bit positions are ?0?). the same restriction for overlapping windows applies in 8?bit mode. ? data classification codes bl, img, crc, and tr codes are defined by the same registers as in 10?bit mode. bits 9:2 of the respective configuration registers are used as classification code with default values shown in table 32. table 32. synchronization channel default identification code values for 8?bit mode sync word bit position register address default value description 7:0 118 [9:2] 0x05 black pixel data (bl). this data is not part of the image. the black pixel data is used internally to correct channel offsets. 7:0 119 [9:2] 0x0d valid pixel data (img). the data on the data output channels is valid pixel data (part of the image). 7:0 125 [9:2] 0x16 crc value. the data on the data output channels is the crc code of the finished image data line. 7:0 126 [9:2] 0xe9 training pattern (tr). the sync channel sends out the training pattern which can be programmed by a register setting.
noip1sn1300a www.onsemi.com 47 training patterns on data channels in 10?bit mode, during idle periods, the data channels transmit training patterns, indicated on the sync channel by a tr code. these training patterns are configurable independent of the training code on the sync channel as shown in table 33. table 33. training code on sync channel in 10?bit mode sync word bit position register address default value description [9:0] 116 [9:0] 0x3a6 data channel training pattern. the data output channels send out the training pattern, which can be programmed by a register setting. the default value of the training pattern is 0x3a6, which is identical to the training pattern indication code on the sync channel. in 8?bit mode, the training pattern for the data channels is defined by the same register as in 10?bit mode, where the lower two bits are omitted; see table 34. table 34. training pattern on data channel in 8?bit mode data word bit position register address default value description [7:0] 116 [9:2] 0xe9 data channel training pattern (training pattern). cyclic redundancy code at the end of each line, a crc code is calculated to allow error detection at the receiving end. each data channel transmits a crc code to protect the data words sent during the previous cycles. idle and training patterns are not included in the calculation. the sync channel is not protected. a special character (crc indication) is transmitted whenever the data channels send their respective crc code. the polynomial in 10?bit operation mode is x 10 +x 9 +x 6 +x 3 +x 2 + x + 1. the crc encoder is seeded at the start of a new line and updated for every (valid) data word received. the crc seed is configurable using the crc_seed register. when ?0?, the crc is seeded by all??0?; when ?1? it is seeded with all??1?. in 8?bit mode, the polynomial is x 8 +x 6 +x 3 +x 2 +1. the crc seed is configured by means of the crc_seed register. note: the crc is calculated for every line. this implies that the crc code can protect lines from multiple windows. lvds output multiplexing the python300, python500 and python1300 image sensors contain a function for down?multiplexing the output channels. using this function, one may for instance use the device with 2 or 1 data channels instead of 4 data channels. enabling the channel multiplexing is done through register 32[5:4]. the default value of 0x0 disables all channel multiplexing. higher values sets a higher degree of channel multiplexing. note that the sync identification codes are repeated multiple times depending on the multiplex factor. the channels that are used per degree of multiplexing and the number of sync code repetitions are shown in table 35. the unused data channels are powered down and will not send any data. table 35. lvds channel multiplexing number of output channels python 300 / python 500 / python 1300 ? lvds channels register 32[5:4] data register 211 data sync code repetitions 4 channels ch 0 ch 1 ch 2 ch 3 0x0 0x0e49 1 2 channels ch 0 ch 2 0x1, 0x2 0x0e39 2 1 channel ch 0 0x3 0x0e29 4 note: the p3?sn/se/fn sensor does not allow the 4 data lane operation. functionality is restricted to 2 or 1 data lane. the mux configuration shall be configured as such.
noip1sn1300a www.onsemi.com 48 data order for p1?sn/se/fn, p3?sn/se/fn: lvds interface version to read out the image data through the output channels, the pixel array is organized in kernels. the kernel size is eight pixels in x?direction by one pixel in y?direction. the data order in 8?bit mode is identical to the 10?bit mode. figure 38 indicates how the kernels are organized. the first kernel (kernel [0, 0]) is located in the bottom left corner. the data order of this image data on the data output channels depends on the subsampling mode. figure 38. kernel organization in pixel array roi kernel (0,0) kernel (159,1023) kernel (x_start,y_start) 0 7 3 2 1 5 6 pixel array ? p1?sn/se/fn, p3?sn/se/fn: subsampling disabled ? 4 lvds output channels (p1 only) the image data is read out in kernels of eight pixels in x?direction by one pixel in y?direction. one data channel output delivers two pixel values of one kernel sequentially. figure 39 shows how a kernel is read out over the four output channels. for even positioned kernels, the kernels are read out ascending, while for odd positioned kernels the data order is reversed (descending). figure 39. p1?sn/se/fn: 4 lvds data output order when subsampling is disabled kernel n?2 kernel n+1 kernel n kernel n?1 0 4 3 2 1 5 7 6 pixel # (even kernel) channel #0 channel #1 channel #3 7 3 4 5 6 2 0 1 pixel # (odd kernel) 10?bit / 8?bit 10?bit / 8?bit msb lsb msb lsb note: the bit order is always msb first channel #2
noip1sn1300a www.onsemi.com 49 ? 2 lvds output channels figure 40 shows how a kernel is read out over 2 output channels. each pair of adjacent channels is multiplexed into one channel. for even positioned kernels, the kernels are read out ascending but in pair of even and odd pixels, while for odd positioned kernels the data order is reversed (descending) but in pair of even and odd pixels. figure 40. p1?sn/se/fn, p3?sn/se/fn: 2 lvds data output order when subsampling is disabled kernel n?2 kernel n+1 kernel n kernel n?1 0 4 3 1 2 6 7 5 pixel # (even kernel) channel #0 7 3 4 6 5 1 0 2 pixel # (odd kernel) 10?bit / 8?bit 10?bit / 8?bit msb lsb msb lsb note: the bit order is always msb first channel #2 ? 1 lvds output channel figure 41 shows how a kernel is read out over 1 output channel. each bunch of four adjacent channels is multiplexed into one channel. for even positioned kernels, the kernels are read out ascending but in sets of 4 even and 4 odd pixels, while for odd positioned kernels the data order is reversed (descending) but in sets of 4 odd and 4 even pixels. figure 41. p1?sn/se/fn, p3?sn/se/fn: 1 lvds data output order when subsampling is disabled kernel n?2 kernel n+1 kernel n kernel n?1 0 1 6 4 2 3 7 5 pixel # (even kernel) channel #0 7 6 1 3 5 4 0 2 pixel # (odd kernel) 10?bit / 8?bit 10?bit / 8?bit msb lsb msb lsb note: the bit order is always msb first
noip1sn1300a www.onsemi.com 50 ? p1?sn/fn, p3?sn/fn: subsampling on monochrome sensor during subsampling on a monochrome sensor, every other pixel is read out and the lines are read in a read-1-skip-1 manner. to read out the image data with subsampling enabled on a monochrome sensor, two neighboring kernels are combined to a single kernel of 16 pixels in the x?direction and one pixel in the y?direction. only the pixels at the even pixel positions inside that kernel are read out. note that there is no difference in data order for even/odd kernel numbers, as opposed to the ?no?subsampling? readout. ? 4 lvds output channels (p1 only) figure 42 shows the data order for 4 lvds output channels. note that there is no difference in data order for even/odd kernel numbers, as opposed to the ?no?subsampling? readout described in previous section. figure 42. p1?sn/fn: data output order for 4 lvds output channels in subsampling mode on a monochrome sensor kernel n?2 kernel n+1 kernel n kernel n?1 0 4 12 2 14 pixel # channel #0 channel #1 channel #2 channel #3 10 6 8 ? 2 lvds output channels figure 43 shows the data order for 2 lvds output channels. note that there is no difference in data order for even/odd kernel numbers, as opposed to the ?no?subsampling? readout described in previous section. figure 43. p1?sn/fn, p3?sn/fn: data output order for 2 lvds output channels in subsampling mode on a monochrome sensor kernel n?2 kernel n+1 kernel n kernel n?1 0 4 12 14 2 pixel # channel #0 channel #2 6 10 8
noip1sn1300a www.onsemi.com 51 ? 1 lvds output channel figure 44 shows the data order for 1 lvds output channel. note that there is no difference in data order for even/odd kernel numbers, as opposed to the ?no?subsampling? readout described in previous section. figure 44. p1?sn/fn, p3?sn/fn: data output order for 1 lvds output channels in subsampling mode on a monochrome sensor kernel n?2 kernel n+1 kernel n kernel n?1 0 14 6 4 2 pixel # channel #0 12 10 8 ? p1?sn/fn, p3?sn/fn: binning on monochrome sensor the output order in binning mode is identical to the subsampled mode. ? p1?se, p3?se: subsampling on color sensor during subsampling on a color sensor, lines are read in a read-2-skip?2 manner. to read out the image data with subsampling enabled on a color sensor, two neighboring kernels are combined to a single kernel of 16 pixels in the x?direction and one pixel in the y?direction. only the pixels 0, 1, 4, 5, 8, 9, 12 and 13 are read out. note that there is no difference in data order for even/odd kernel numbers, as opposed to the ?no?subsampling? readout. ? 4 lvds output channels (p1 only) figure 45 shows the data order for 4 lvds output channels. note that there is no difference in data order for even/odd kernel numbers, as opposed to the ?no?subsampling? readout described in previous section. figure 45. p1?se: data output order for 4 lvds output channels in subsampling mode on a color sensor kernel n?2 kernel n+1 kernel n kernel n?1 0 4 12 13 1 pixel # channel #0 channel #1 channel #2 channel #3 5 9 8
noip1sn1300a www.onsemi.com 52 ? 2 lvds output channels figure 46 shows the data order for 2 lvds output channels. note that there is no difference in data order for even/odd kernel numbers, as opposed to the ?no?subsampling? readout described in previous section. figure 46. p1?se, p3?se: data output order for 2 lvds output channels in subsampling mode on a color senso r kernel n?2 kernel n+1 kernel n kernel n?1 0 4 12 1 13 pixel # channel #0 channel #2 9 5 8 ? 1 lvds output channel figure 47 shows the data order for 1 lvds output channel. note that there is no difference in data order for even/odd kernel numbers, as opposed to the ?no?subsampling? readout described in previous section. figure 47. p1?se, p3?se: data output order for 1 lvds output channel in subsampling mode on a color senso r kernel n?2 kernel n+1 kernel n kernel n?1 0 1 9 4 13 pixel # channel #0 12 5 8
noip1sn1300a www.onsemi.com 53 p2?sn/se: cmos interface version cmos output signals the image data output occurs through a single 10?bit parallel cmos data output, operating at the applied clk_pll frequency. a cmos clock output, ?frame valid? and ?line valid? signal synchronizes the output data. no windowing information is sent out by the sensor. 8?bit/10?bit mode the 8?bit mode is not supported when using the parallel cmos output interface. frame format frame timing is indicated by means of two signals: frame_valid and line_valid. ? the frame_valid indication is asserted at the start of a new frame and remains asserted until the last line of the frame is completely transmitted. ? the line_valid indication serves the following needs: ? while the line_valid indication is asserted, the data channels contain valid pixel data. ? the line valid communicates frame timing as it is asserted at the start of each line and it is de?asserted at the end of the line. low periods indicate the idle time between lines (rot). ? the data channels transmit the calculated crc code after each line. this can be detected as the data words right after the falling edge of the line valid. figure 48. p2?sn/se/fn: frame timing indication data channels sequencer internal state line ys line ys+1 line ye black fot rot rot rot rot fot rot black frame_valid line_valid
noip1sn1300a www.onsemi.com 54 the frame format is explained with an example of the readout of two (overlapping) windows as shown in figure 49 (a). the readout of a frame occurs on a line?by?line basis. the read pointer goes from left to right, bottom to top. figure 49 (a) and (b) indicate that, after the fot is finished, a number of lines which include information of ?roi 0? are sent out, starting at position y0_start. when the line at position y1_start is reached, a number of lines containing data of ?roi 0? and ?roi 1? are sent out, until the line position of y0_end is reached. then, only data of ?roi 1? appears on the data output until line position y1_end is reached. the line_valid strobe is not shown in figure 49. figure 49. p2?sn/se: frame format to read out image data (a) (b) 1280 pixels y0_start y1_start y0_end y1_end x0_start x1_start x0_end x1_end roi0 roi 1 reset n exposure time n reset n+1 exposure time n +1 roi0 fot fot integration time handling readout handling fot readout frame n -1 readout frame n roi 0 roi1 frame valid fot fot roi1 pixels 1024 black lines black pixel data is also sent through the data channels. to distinguish these pixels from the regular image data, it is possible to ?mute? the frame and/or line valid indications for the black lines. refer to t able 36 for black line, frame_valid and line_valid settings. table 36. black line frame_valid and line_valid settings bl_frame _valid_enable bl_line _valid_enable description 0x1 0x1 the black lines are handled similar to normal image lines. the frame valid indication is asserted before the first black line and the line valid indication is asserted for every valid (black) pixel. 0x1 0x0 the frame valid indication is asserted before the first black line, but the line valid indication is not asserted for the black lines. the line valid indication indicates the valid image pixels only. this mode is useful when one does not use the black pixels and when the frame valid indication needs to be asserted some time before the first image lines (for example, to precondition isp pipelines). 0x0 0x1 in this mode, the black pixel data is clearly unambiguously indicated by the line valid indication, while the decoding of the real image data is simplified. 0x0 0x0 black lines are not indicated and frame and line valid strobes remain de?asserted. note however that the data channels contains the black pixel data and crc codes (training patterns are interrupted).
noip1sn1300a www.onsemi.com 55 data order for p2?sn/se: cmos interface version to read out the image data through the parallel cmos output, the pixel array is divided in kernels. the kernel size is eight pixels in x?direction by one pixel in y?direction. figure 38 on page 48 indicates how the kernels are organized. the data order of this image data on the data output channels depends on the subsampling mode. ? p2?sn/se: no subsampling the image data is read out in kernels of eight pixels in x?direction by one pixel in y?direction. figure 50 shows the pixel sequence of a kernel which is read out over the single cmos output channel. the pixel order is different for even and odd kernel positions. figure 50. p2?sn/se: data output order without subsampling kernel 12 kernel 15 kernel 14 kernel 13 0 1 6 4 2 3 7 5 pixel # (even kernel) 7 6 1 3 5 4 0 2 pixel # (odd kernel) time time ? p2?sn: subsampling on monochrome sensor to read out the image data with subsampling enabled on a monochrome sensor, two neighboring kernels are combined to a single kernel of 16 pixels in the x?direction and one pixel in the y?direction. only the pixels at the even pixel positions inside that kernel are read out. figure 51 shows the data order note that there is no difference in data order for even/odd kernel numbers, as opposed to the ?no?subsampling? readout. figure 51. p2?sn: data output order with subsampling on a monochrome sensor kernel 12 kernel 15 kernel 14 kernel 13 0 14 6 4 2 12 8 10 pixel # time time ? p2?se: subsampling on color sensor to read out the image data with subsampling enabled on a color sensor, two neighboring kernels are combined to a single kernel of 16 pixels in the x?direction and one pixel in the y?direction. only the pixels 0, 1, 4, 5, 8, 9, 12, and 13 are read out. figure 52 shows the data order. note that there is no difference in data order for even/odd kernel numbers, as opposed to the ?no?subsampling? readout. figure 52. p2?se: data output order with subsampling on a color sensor kernel 12 kernel 15 kernel 14 kernel 13 0 1 9 4 13 12 8 5 pixel # time time
noip1sn1300a www.onsemi.com 56 register map the table below represents the register map for the noip1xx1300a part. deviating default values for the noip1xx0500a and noip1xx0300a are mentioned between brackets (?[ ]?). table 37. register map address offset address bit field register name default (hex) default description type chip id [block offset: 0] 0 0 chip_id 0x50d0 20688 chip id status [15:0] id 0x50d0 20688 chip id 1 1 reserved 0x0001 0x0201 0x0101 1 [513, 257] reserved status [3:0] reserved 0x1 1 reserved [9:8] resolution 0x0 [0x2, 0x1] 0 [2, 1] sensor resolution 0x0: python1300, 0x1: python300 0x2: python500 [11:10] reserved 0x0 0 reserved 2 2 chip_configuration 0x0000 0 chip general configuration rw [0] color 0x0 0 color/monochrome configuration ?0?: monochrome ?1?: color [1] parallel 0x0 0 lvds/parallel mode selector ?0?: lvds ?1?: parallel reset generator [block offset: 8] 0 8 soft_reset_pll 0x0099 153 pll soft reset configuration rw [3:0] pll_soft_reset 0x9 9 pll reset 0x9: soft reset state others: operational [7:4] pll_lock_soft_reset 0x9 9 pll lock detect reset 0x9: soft reset state others: operational 1 9 soft_reset_cgen 0x0009 9 clock generator soft reset rw [3:0] cgen_soft_reset 0x9 9 clock generator reset 0x9: soft reset state others: operational 2 10 soft_reset_analog 0x0999 2457 analog block soft reset rw [3:0] mux_soft_reset 0x9 9 column mux reset 0x9: soft reset state others: operational [7:4] afe_soft_reset 0x9 9 afe reset 0x9: soft reset state others: operational [11:8] ser_soft_reset 0x9 9 serializer reset 0x9: soft reset state others: operational pll [block offset: 16] 0 16 power_down 0x0004 4 pll configuration rw [0] pwd_n 0x0 0 pll power down ?0?: power down, ?1?: operational [1] enable 0x0 0 pll enable ?0?: disabled, ?1?: enabled [2] bypass 0x1 1 pll bypass ?0?: pll active, ?1?: pll bypassed
noip1sn1300a www.onsemi.com 57 table 37. register map address offset type description default default (hex) register name bit field address 1 17 reserved 0x2113 8467 reserved rw [7:0] reserved 0x13 19 reserved [12:8] reserved 0x1 1 reserved [14:13] reserved 0x1 1 reserved i/o [block offset: 20] 0 20 config1 0x0000 0 io configuration rw [0] clock_in_pwd_n 0x0 0 power down clock input [9:8] reserved 0x0 0 reserved [10] reserved 0x0 0 reserved pll lock detector [block offset: 24] 0 24 pll_lock 0x0000 0 pll lock indication status [0] lock 0x0 0 pll lock indication 2 26 reserved 0x2280 8832 reserved rw [7:0] reserved 0x80 128 reserved [10:8] reserved 0x2 2 reserved [14:12] reserved 0x2 2 reserved 3 27 reserved 0x3d2d 15661 reserved rw [7:0] reserved 0x2d 45 reserved [15:8] reserved 0x3d 61 reserved clock generator [block offset: 32] 0 32 config0 0x0004 4 clock generator configuration rw [0] enable_analog 0x0 0 enable analogue clocks ?0?: disabled, ?1?: enabled [1] enable_log 0x0 0 enable logic clock ?0?: disabled, ?1?: enabled [2] select_pll 0x1 1 input clock selection ?0?: select lvds clock input, ?1?: select pll clock input [3] adc_mode 0x0 0 set operation mode of cgen block ?0?: divide by 5 mode (10-bit mode), ?1?: divide by 4 mode (8-bit mode) [5:4] mux 0x0 0 multiplex mode [11:8] reserved 0x0 0 reserved [14:12] reserved 0x0 0 reserved general logic [block offset: 34] 0 34 config0 0x0000 0 clock generator configuration rw [0] enable 0x0 0 logic general enable configuration ?0?: disable ?1?: enable image core [block offset: 40] 0 40 image_core_config0 0x0000 0 image core configuration rw [0] imc_pwd_n 0x0 0 image core power down ?0?: powered down, ?1?: powered up [1] mux_pwd_n 0x0 0 column multiplexer power down ?0?: powered down, ?1?: powered up
noip1sn1300a www.onsemi.com 58 table 37. register map address offset type description default default (hex) register name bit field address [2] colbias_enable 0x0 0 bias enable ?0?: disabled ?1?: enabled 1 41 image_core_config1 0x0b5a 2906 image core configuration rw [3:0] dac_ds 0xa 10 double slope reset level [7:4] dac_ts 0x5 5 triple slope reset level [10:8] reserved 0x3 3 reserved [12:11] reserved 0x1 1 reserved [13] reserved 0x0 0 reserved [14] reserved 0x0 0 reserved [15] reserved 0x0 0 reserved 2 42 reserved 0x0001 1 reserved rw [0] reserved 0x1 1 reserved [1] reserved 0x0 0 reserved [6:4] reserved 0x0 0 reserved [10:8] reserved 0x0 0 reserved [15:12] reserved 0x0 0 reserved 3 43 reserved 0x0000 0 reserved rw [0] reserved 0x0 0 reserved [1] reserved 0x0 0 reserved [2] reserved 0x0 0 reserved [3] reserved 0x0 0 reserved [6:4] reserved 0x0 0 reserved [15:7] reserved 0x0 0 reserved afe [block offset: 48] 0 48 power_down 0x0000 0 afe configuration rw [0] pwd_n 0x0 0 power down for afe?s ?0?: powered down, ?1?: powered up bias [block offset: 64] 0 64 power_down 0x0000 0 bias power down configuration rw [0] pwd_n 0x0 0 power down bandgap ?0?: powered down, ?1?: powered up 1 65 configuration 0x888b 34955 bias configuration rw [0] extres 0x1 1 external resistor selection ?0?: internal resistor, ?1?: external resistor [3:1] reserved 0x5 5 reserved [7:4] imc_colpc_ibias 0x8 8 column precharge ibias configuration [11:8] imc_colbias_ibias 0x8 8 column bias ibias configuration [15:12] cp_ibias 0x8 8 charge pump bias 2 66 afe_bias 0x53c8 21448 afe bias configuration rw [3:0] afe_ibias 0x8 8 afe ibias configuration [7:4] afe_adc_iref 0xc 12 adc iref configuration [14:8] afe_pga_iref 0x53 83 pga iref configuration 3 67 mux_bias 0x8888 34952 column multiplexer bias configuration rw [3:0] mux_25u_stage1 0x8 8 column multiplexer stage 1 bias configuration
noip1sn1300a www.onsemi.com 59 table 37. register map address offset type description default default (hex) register name bit field address [7:4] mux_25u_stage2 0x8 8 column multiplexer stage 2 bias configuration [11:8] mux_25u_delay 0x8 8 column multiplexer delay bias configuration [15:12] reserved 0x8 8 reserved 4 68 lvds_bias 0x0088 136 lvds bias configuration rw [3:0] lvds_ibias 0x8 8 lvds ibias [7:4] lvds_iref 0x8 8 lvds iref 5 69 adc_bias 0x0088 136 lvds bias configuration rw [3:0] imc_vsfdmed_ibias 0x8 8 vsfd medium bias [7:4] adcref_ibias 0x8 8 adc reference bias 6 70 reserved 0x8888 34952 reserved rw [3:0] reserved 0x8 8 reserved [7:4] reserved 0x8 8 reserved [11:8] reserved 0x8 8 reserved [15:12] reserved 0x8 8 reserved 7 71 reserved 0x8888 34952 reserved rw [15:0] reserved 0x8888 34952 reserved charge pump [block offset: 72] 0 72 configuration 0x2220 8736 charge pump configuration rw [0] trans_pwd_n 0x0 0 pd trans charge pump enable ?0?: disabled, ?1?: enabled [1] resfd_calib_pwd_n 0x0 0 fd charge pump enable ?0?: disabled, ?1?: enabled [2] sel_sample_pwd_n 0x0 0 select/sample charge pump enable ?0?: disabled ?1?: enabled [6:4] trans_trim 0x2 2 pd trans charge pump trim [10:8] resfd_calib_trim 0x2 2 fd charge pump trim [14:12] sel_sample_trim 0x2 2 select/sample charge pump trim charge pump [block offset: 80] reserved reserved 0 80 reserved 0x0000 0 reserved rw [1:0] reserved 0x0 0 reserved [3:2] reserved 0x0 0 reserved [5:4] reserved 0x0 0 reserved [7:6] reserved 0x0 0 reserved [9:8] reserved 0x0 0 reserved 1 81 reserved 0x8881 34945 reserved rw [15:0] reserved 0x8881 34945 reserved temperature sensor [block offset: 96] 0 96 enable 0x0000 0 temperature sensor configuration rw [0] enable 0x0 0 temperature diode enable ?0?: disabled, ?1?: enabled [1] reserved 0x0 0 reserved [2] reserved 0x0 0 reserved
noip1sn1300a www.onsemi.com 60 table 37. register map address offset type description default default (hex) register name bit field address [3] reserved 0x0 0 reserved [4] reserved 0x0 0 reserved [5] reserved 0x0 0 reserved [13:8] offset 0x0 0 temperature offset (signed) 1 97 temp 0x0000 0 temperature sensor status status [7:0] temp 0x00 0 temperature readout reserved [block offset: 104] reserved reserved 0 104 reserved 0x0000 0 reserved rw [15:0] reserved 0x0 0 reserved 1 105 reserved 0x0000 0 reserved rw [1:0] reserved 0x0 0 reserved [6:2] reserved 0x0 0 reserved [7] reserved 0x0 0 reserved [9:8] reserved 0x0 0 reserved [14:10] reserved 0x0 0 reserved [15] reserved 0x0 0 reserved 2 106 reserved 0x0000 0 reserved status [15:0] reserved 0x0000 0 reserved 3 107 reserved 0x0000 0 reserved status [15:0] reserved 0x0000 0 reserved 4 108 reserved 0x0000 0 reserved status [15:0] reserved 0x0000 0 reserved 5 109 reserved 0x0000 0 reserved status [15:0] reserved 0x0000 0 reserved 6 110 reserved 0x0000 0 reserved status [15:0] reserved 0x0000 0 reserved 7 111 reserved 0x0000 0 reserved status [15:0] reserved 0x0000 0 reserved serializers/lvds/io [block offset: 112] 0 112 power_down 0x0000 0 lvds power down configuration rw [0] clock_out_pwd_n 0x0 0 power down for clock output. ?0 ?: powered down, ?1?: powered up [1] sync_pwd_n 0x0 0 power down for sync channel ?0?: powered down, ?1?: powered up [2] data_pwd_n 0x0 0 power down for data channels (4 channels) ?0?: powered down, ?1?: powered up sync words [block offset: 116] 4 116 trainingpattern 0x03a6 934 data formating - training pattern rw [9:0] trainingpattern 0x3a6 934 training pattern sent on data channels during idle mode. this data is used to perform word alignment on the lvds data channels. 5 117 sync_code0 0x002a 42 lvds power down configuration rw [6:0] frame_sync_0 0x02a 42 frame sync code lsbs - even kernels
noip1sn1300a www.onsemi.com 61 table 37. register map address offset type description default default (hex) register name bit field address 6 118 sync_code1 0x0015 21 data formating - bl indication rw [9:0] bl_0 0x015 21 black pixel identification sync code - even kernels 7 119 sync_code2 0x0035 53 data formating - img indication rw [9:0] img_0 0x035 53 valid pixel identification sync code - even kernels 8 120 sync_code3 0x0025 37 data formating - img indication rw [9:0] ref_0 0x025 37 reference pixel identification sync code - even kernels 9 121 sync_code4 0x002a 42 lvds power down configuration rw [6:0] frame_sync_1 0x02a 42 frame sync code lsbs - odd kernels 10 122 sync_code5 0x0015 21 data formating - bl indication rw [9:0] bl_1 0x015 21 black pixel identification sync code - odd kernels 11 123 sync_code6 0x0035 53 data formating - img indication rw [9:0] img_1 0x035 53 valid pixel identification sync code - odd kernels 12 124 sync_code7 0x0025 37 data formating - img indication rw [9:0] ref_1 0x025 37 reference pixel identification sync code - odd kernels 13 125 sync_code8 0x0059 89 data formating - crc indication rw [9:0] crc 0x059 89 crc value identification sync code 14 126 sync_code9 0x03a6 934 data formating - tr indication rw [9:0] tr 0x3a6 934 training value identification sync code data block [block offset: 128] 0 128 blackcal 0x4008 16392 black calibration configuration rw [7:0] black_offset 0x08 8 desired black level at output [10:8] black_samples 0x0 0 black pixels taken into account for black calibration. total samples = 2**black_samples [14:11] reserved 0x8 8 reserved [15] crc_seed 0x0 0 crc seed ?0?: all-0 ?1?: all-1 1 129 general_configuration 0x0001 1 black calibration and data formating configuration rw [0] auto_blackcal_enable 0x1 1 automatic blackcalibration is enabled when 1, bypassed when 0 [9:1] blackcal_offset 0x00 0 black calibration offset used when au- to_black_cal_en = ?0?. [10] blackcal_offset_dec 0x0 0 blackcal_offset is added when 0, subtracted when 1 [11] reserved 0x0 0 reserved [12] reserved 0x0 0 reserved [13] 8bit_mode 0x0 0 shifts window id indications by 4 cycles. ?0?: 10 bit mode, ?1?: 8 bit mode [14] ref_mode 0x0 0 data contained on reference lines: ?0?: reference pixels ?1?: black average for the corresponding data channel [15] ref_bcal_enable 0x0 0 enable black calibration on reference lines ?0?: disabled ?1?: enabled
noip1sn1300a www.onsemi.com 62 table 37. register map address offset type description default default (hex) register name bit field address 2 130 trainingpattern 0x000f 15 data formating - training pattern rw [0] bl_frame_valid_en- able 0x1 1 assert frame_valid for black lines when ?1?, gate frame_valid for black lines when ?0?. parallel output mode only. [1] bl_line_valid_enable 0x1 1 assert line_valid for black lines when ?1?, gate line_valid for black lines when ?0?. parallel output mode only. [2] ref_frame_valid_en- able 0x1 1 assert frame_valid for ref lines when ?1?, gate frame_valid for black lines when ?0?. parallel output mode only. [3] ref_line_valid_enable 0x1 1 assert line_valid for ref lines when ?1?, gate line_valid for black lines when ?0?. parallel output mode only. [4] frame_valid_mode 0x0 0 behaviour of frame_valid strobe between overhead lines when [0] and/or [1] is deasserted: ?0?: retain frame_valid deasserted between lines ?1?: assert frame_valid between lines [8] reserved 0x0 0 reserved 8 136 blackcal_error0 0x0000 0 black calibration status status [15:0] blackcal_error[15:0] 0x0000 0 black calibration error. this flag is set when not enough black samples are availlable. black calibration shall not be valid. channels 0-16 (channels 0-7 for python1300) 9 137 reserved 0x0000 0 reserved status [15:0] reserved 0x0000 0 reserved 10 138 reserved 0x0000 0 reserved status [15:0] reserved 0x0000 0 reserved 11 139 reserved 0x0000 0 reserved status [15:0] reserved 0x0000 0 reserved 12 140 reserved 0x0000 0 reserved rw [15:0] reserved 0x0000 0 reserved 13 141 reserved 0xffff 65535 reserved rw [15:0] reserved 0xffff 65535 reserved 16 144 test_configuration 0x0000 0 data formating test configuration rw [0] testpattern_en 0x0 0 insert synthesized testpattern when ?1? [1] inc_testpattern 0x0 0 incrementing testpattern when ?1?, constant testpattern when ?0? [2] prbs_en 0x0 0 insert prbs when ?1? [3] frame_testpattern 0x0 0 frame test patterns when ?1?, unframed test- patterns when ?0? [4] reserved 0x0 0 reserved 17 145 reserved 0x0000 0 reserved rw [15:0] reserved reserved 18 146 test_configuration0 0x0100 256 data formating test configuration rw [7:0] testpattern0_lsb 0x00 0 testpattern used on datapath #0 when testpattern_en = ?1?. note: most significant bits are configured in register 150. [15:8] testpattern1_lsb 0x01 1 testpattern used on datapath #1 when testpattern_en = ?1?. note: most significant bits are configured in register 150.
noip1sn1300a www.onsemi.com 63 table 37. register map address offset type description default default (hex) register name bit field address 19 147 test_configuration1 0x0302 770 data formating test configuration rw [7:0] testpattern2_lsb 0x02 2 testpattern used on datapath #2 when testpattern_en = ?1?. note: most significant bits are configured in register 150. [15:8] testpattern3_lsb 0x03 3 testpattern used on datapath #3 when testpattern_en = ?1?. note: most significant bits are configured in register 150. 20 148 reserved 0x0504 1284 reserved rw [7:0] reserved 0x04 4 reserved [15:8] reserved 0x05 5 reserved 21 149 reserved 0x0706 1798 reserved rw [7:0] reserved 0x06 6 reserved [15:8] reserved 0x07 7 reserved 22 150 test_configuration16 0x0000 0 data formating test configuration rw [1:0] testpattern0_msb 0x0 0 testpattern used when testpattern_en = ?1? [3:2] testpattern1_msb 0x0 0 testpattern used when testpattern_en = ?1? [5:4] testpattern2_msb 0x0 0 testpattern used when testpattern_en = ?1? [7:6] testpattern3_msb 0x0 0 testpattern used when testpattern_en = ?1? [9:8] reserved 0x0 0 reserved [11:10] reserved 0x0 0 reserved [13:12] reserved 0x0 0 reserved [15:14] reserved 0x0 0 reserved 26 154 reserved 0x0000 0 reserved rw [15:0] reserved 0x0000 0 reserved 27 155 reserved 0x0000 0 reserved rw [15:0] reserved 0x0000 0 reserved aec [block offset: 160] 0 160 configuration 0x0010 16 aec configuration rw [0] enable 0x0 0 aec enable [1] restart_filter 0x0 0 restart aec filter [2] freeze 0x0 0 freeze aec filter and enforcer gains [3] pixel_valid 0x0 0 use every pixel from channel when 0, every 4th pixel when 1 [4] amp_pri 0x1 1 column amplifier gets higher priority than afe pga in gain distribution if 1. vice versa if 0 1 161 intensity 0x60b8 24760 aec configuration rw [9:0] desired_intensity 0xb8 184 target average intensity [15:10] reserved 0x018 24 reserved 2 162 red_scale_factor 0x0080 128 red scale factor rw [9:0] red_scale_factor 0x80 128 red scale factor 3.7 unsigned 3 163 green1_scale_factor 0x0080 128 green1 scale factor rw [9:0] green1_scale_factor 0x80 128 green1 scale factor 3.7 unsigned 4 164 green2_scale_factor 0x0080 128 green2 scale factor rw [9:0] green2_scale_factor 0x80 128 green2 scale factor 3.7 unsigned
noip1sn1300a www.onsemi.com 64 table 37. register map address offset type description default default (hex) register name bit field address 5 165 blue_scale_factor 0x0080 128 blue scale factor rw [9:0] blue_scale_factor 0x80 128 blue scale factor 3.7 unsigned 6 166 reserved 0x03ff 1023 reserved rw [15:0] reserved 0x03ff 1023 reserved 7 167 reserved 0x0080 2048 reserved rw [1:0] reserved 0x0 0 reserved [3:2] reserved 0x0 0 reserved [15:4] reserved 0x080 128 reserved 8 168 min_exposure 0x0001 1 minimum exposure time rw [15:0] min_exposure 0x0001 1 minimum exposure time 9 169 min_gain 0x0800 2048 minimum gain rw [1:0] min_mux_gain 0x0 0 minimum column amplifier gain [3:2] min_afe_gain 0x0 0 minimum afe pga gain [15:4] min_digital_gain 0x080 128 minimum digital gain 5.7 unsigned 10 170 max_exposure 0x03ff 1023 maximum exposure time rw [15:0] max_exposure 0x03ff 1023 maximum exposure time 11 171 max_gain 0x100d 4109 maximum gain rw [1:0] max_mux_gain 0x1 1 maximum column amplifier gain [3:2] max_afe_gain 0x3 3 maximum afe pga gain [15:4] max_digital_gain 0x100 256 maximum digital gain 5.7 unsigned 12 172 reserved 0x0083 131 reserved rw [7:0] reserved 0x083 131 reserved [13:8] reserved 0x00 0 reserved [15:14] reserved 0x0 0 reserved 13 173 reserved 0x2824 10276 reserved rw [7:0] reserved 0x024 36 reserved [15:8] reserved 0x028 40 reserved 14 174 reserved 0x2a96 10902 reserved rw [3:0] reserved 0x6 6 reserved [7:4] reserved 0x9 9 reserved [11:8] reserved 0xa 10 reserved [15:12] reserved 0x2 2 reserved 15 175 reserved 0x0080 128 reserved rw [9:0] reserved 0x080 128 reserved 16 176 reserved 0x0100 256 reserved rw [9:0] reserved 0x100 256 reserved 17 177 reserved 0x0100 256 reserved rw [9:0] reserved 0x100 256 reserved 18 178 reserved 0x0080 128 reserved rw [9:0] reserved 0x080 128 reserved 19 179 reserved 0x00aa 170 reserved rw [9:0] reserved 0x0aa 170 reserved
noip1sn1300a www.onsemi.com 65 table 37. register map address offset type description default default (hex) register name bit field address 20 180 reserved 0x0100 256 reserved rw [9:0] reserved 0x100 256 reserved 21 181 reserved 0x0155 341 reserved rw [9:0] reserved 0x155 341 reserved 24 184 total_pixels0 0x0000 0 aec status status [15:0] total_pixels[15:0] 0x0000 0 total number of pixels sampled for average, lsb 25 185 total_pixels1 0x0000 0 aec status status [7:0] total_pixels[23:16] 0x0 0 total number of pixels sampled for average, msb 26 186 average_status 0x0000 0 ase status status [9:0] average 0x000 0 aec average status [12] avg_locked 0x0 0 aec average lock status 27 187 exposure_status 0x0000 0 ase status status [15:0] exposure 0x0000 0 aec exposure status 28 188 gain_status 0x0000 0 ase status status [1:0] mux_gain 0x0 0 aec mux gain status [3:2] afe_gain 0x0 0 aec afe gain status [15:4] digital_gain 0x000 0 aec digital gain status 5.7 unsigned 29 189 reserved 0x0000 0 reserved status [12:0] reserved 0x000 0 reserved [13] reserved 0x0 0 reserved sequencer [block offset: 192] 0 192 general_configuration 0x0000 0 sequencer general configuration rw [0] enable 0x0 0 enable sequencer ?0?: idle, ?1?: enabled [1] operation selection 0x0 0 ?0?: global shutter [2] zero_rot_enable 0x0 0 zero rot mode selection. ?0?: normal rot, ?1?: zero rot? [3] reserved 0x0 0 reserved [4] triggered_mode 0x0 0 triggered mode selection ?0?: normal mode, ?1?: triggered mode [5] slave_mode 0x0 0 master/slave selection ?0?: master, ?1?: slave [6] nzrot_xsm_delay_en- able 0x0 0 insert delay between end of rot and start of readout in normal rot readout mode if ?1?. rot delay is defined by register xsm_delay [7] subsampling 0x0 0 subsampling mode selection ?0?: no subsampling, ?1?: subsampling [8] binning 0x0 0 binning mode selection ?0?: no binning, ?1?: binning [10] roi_aec_enable 0x0 0 enable windowing for aec statistics. ?0?: subsample all windows ?1?: subsample configured window [13:11] monitor_select 0x0 0 control of the monitor pins [14] reserved 0x0 0 reserved
noip1sn1300a www.onsemi.com 66 table 37. register map address offset type description default default (hex) register name bit field address [15] reserved 0x0 0 reserved 1 193 delay_configuration 0x0000 0 sequencer delay configuration rw [7:0] reserved 0x00 0 reserved [15:8] xsm_delay 0x00 0 delay between rot start and x-readout (zero rot mode) delay between rot end and x-readout (normal rot mode with nzrot_xsm_delay_enable=?1?) 2 194 integration_control 0x00e4 228 integration control rw [0] dual_slope_enable 0x0 0 enable dual slope [1] triple_slope_enable 0x0 0 enable triple slope [2] fr_mode 0x1 1 representation of fr_length. ?0?: reset length ?1?: frame length [4] int_priority 0x0 0 integration priority ?0?: frame readout has priority over integration ?1?: integration end has priority over frame readout [5] halt_mode 0x1 1 the current frame will be completed when the sequencer is disabled and halt_mode = ?1?. when ?0?, the sensor stops immediately when disabled, without finishing the current frame. [6] fss_enable 0x1 1 generation of frame sequence start sync code (fss) ?0?: no generation of fss ?1?: generation of fss [7] fse_enable 0x1 1 generation of frame sequence end sync code (fse) ?0?: no generation of fse ?1?: generation of fse [8] reverse_y 0x0 0 reverse readout ?0?: bottom to top readout ?1?: top to bottom readout [9] reserved 0x0 0 reserved [11:10] subsampling_mode 0x0 0 subsampling mode ?00?: subsampling in x and y (vita compatible) ?01?: subsampling in x, not y ?10?: subsampling in y, not x ?11?: subsampling in x an y [13:12] binning_mode 0x0 0 binning mode ?00?: binning in x and y (vita compatible) ?01?: binning in x, not y ?10?: binning in y, not x ?11?: binning in x an y [14] reserved 0x0 0 reserved [15] reserved 0x0 0 reserved 3 195 roi_active0_0 0x0001 1 active roi selection rw [7:0] roi_active0[7:0] 0x01 1 active roi selection [0] roi0 active [1] roi1 active ... [7] roi7 active 4 196 reserved 0x0000 0 reserved rw [15:0] reserved 0x0000 0 reserved 5 197 black_lines 0x0102 258 black line configuration rw [7:0] black_lines 0x02 2 number of black lines. minimum is 1. range 1-255
noip1sn1300a www.onsemi.com 67 table 37. register map address offset type description default default (hex) register name bit field address [12:8] gate_first_line 0x1 1 blank out first lines 0: no blank 1-31: blank 1-31 lines 6 198 reserved 0x0000 0 reserved rw [11:0] reserved 0x000 0 reserved 7 199 mult_timer0 0x0001 1 exposure/frame rate configuration rw [15:0] mult_timer0 0x0001 1 mult timer defines granularity (unit = 1/pll clock) of exposure and reset_length 8 200 fr_length0 0x0000 0 exposure/frame rate configuration rw [15:0] fr_length0 0x0000 0 frame/reset length reset length when fr_mode = ?0?, frame length when fr_mode = ?1? granularity defined by mult_timer 9 201 exposure0 0x0000 0 exposure/frame rate configuration rw [15:0] exposure0 0x0000 0 exposure time granularity defined by mult_timer 10 202 exposure_ds0 0x0000 0 exposure/frame rate configuration rw [15:0] exposure_ds0 0x0000 0 exposure time (dual slope) granularity defined by mult_timer 11 203 exposure_ts0 0x0000 0 exposure/frame rate configuration rw [15:0] exposure_ts0 0x0000 0 exposure time (triple slope) granularity defined by mult_timer 12 204 gain_configuration0 0x01e3 483 gain configuration rw [4:0] mux_gainsw0 0x03 3 column gain setting [12:5] afe_gain0 0xf 15 afe programmable gain setting [13] gain_lat_comp 0x0 0 postpone gain update by 1 frame when ?1? to compensate for exposure time updates laten- cy. gain is applied at start of next frame if ?0? 13 205 digital_gain _configuration0 0x0080 128 gain configuration rw [11:0] db_gain0 0x080 128 digital gain 14 206 sync_configuration 0x037f 895 synchronization configuration rw [0] sync_rs_x_length 0x1 1 update of rs_x_length will not be sync?ed at start of frame when ?0? [1] sync_black_lines 0x1 1 update of black_lines will not be sync?ed at start of frame when ?0? [2] sync_dummy_lines 0x1 1 update of dummy_lines will not be sync?ed at start of frame when ?0? [3] sync_exposure 0x1 1 update of exposure will not be sync?ed at start of frame when ?0? [4] sync_gain 0x1 1 update of gain settings (gain_sw, afe_gain) will not be sync?ed at start of frame when ?0? [5] sync_roi 0x1 1 update of roi updates (active_roi) will not be sync?ed at start of frame when ?0? [6] sync_ref_lines 0x1 1 update of ref_lines will not be sync?ed at start of frame when ?0? [8] blank_roi_switch 0x1 1 blank first frame after roi switching [9] blank _subsampling_ss 0x1 1 blank first frame after subsampling/binning mode.
noip1sn1300a www.onsemi.com 68 table 37. register map address offset type description default default (hex) register name bit field address [10] expos- ure_sync_mode 0x0 0 when ?0?, exposure configurations are sync?ed at the start of fot. when ?1?, exposure configurations sync is disabled (continuously syncing). this mode is only relevant for trig- gered snapshot - master mode, where the ex- posure configurations are sync?ed at the start of exposure rather than the start of fot. for all other modes it should be set to ?0?. note: sync is still postponed if sync_exposure=?0?. 15 207 ref_lines 0x0000 0 reference line configuration rw [7:0] ref_lines 0x00 0 number of reference lines 0-255 16 208 reserved 0x9f00 40704 reserved rw [7:0] reserved 0x00 0 reserved [15:8] reserved 0x9f 159 reserved 19 211 reserved 0x0e5b 3675 reserved rw [0] reserved 0x1 1 reserved [1] reserved 0x1 1 reserved [2] reserved 0x0 0 reserved [3] reserved 0x1 1 reserved [6:4] reserved 0x5 5 reserved [15:8] reserved 0xe 14 reserved 20 212 reserved 0x0000 0 reserved rw [12:0] reserved 0x0000 0 reserved [15] reserved 0x0 0 reserved 21 213 reserved 0x03ff 1023 reserved rw [12:0] reserved 0x03ff 1023 reserved 22 214 reserved 0x0000 0 reserved rw [7:0] reserved 0x00 0 reserved [15:8] reserved 0x0 0 reserved 23 215 reserved 0x0103 259 reserved rw [0] reserved 0x1 1 reserved [1] reserved 0x1 1 reserved [2] reserved 0x0 0 reserved [3] reserved 0x0 0 reserved [4] reserved 0x0 0 reserved [5] reserved 0x0 0 reserved [6] reserved 0x0 0 reserved [7] reserved 0x0 0 reserved [8] reserved 0x1 1 reserved [9] reserved 0x0 0 reserved [10] reserved 0x0 0 reserved [11] reserved 0x0 0 reserved [12] reserved 0x0 0 reserved [13] reserved 0x0 0 reserved [14] reserved 0x0 0 reserved 24 216 reserved 0x7f08 32520 reserved rw [6:0] reserved 0x08 8 reserved
noip1sn1300a www.onsemi.com 69 table 37. register map address offset type description default default (hex) register name bit field address [14:8] reserved 0x7f 127 reserved 25 217 reserved 0x4444 17476 reserved rw [6:0] reserved 0x44 68 reserved [14:8] reserved 0x44 68 reserved 26 218 reserved 0x4444 17476 reserved rw [6:0] reserved 0x44 68 reserved [14:8] reserved 0x44 68 reserved 27 219 reserved 0x0016 22 reserved rw [6:0] reserved 0x016 22 reserved [14:8] reserved 0x00 0 reserved 28 220 lsm_prog_base_ss 0x301f 12319 sequencer program configuration rw [6:0] lsm_prog_base_ss 0x1f 31 lsm program start for non?black lines in snapshot shutter mode [14:8] lsm_black_prog_base _ss 0x30 48 lsm program start for black lines in snapshot shutter mode 29 221 reserved 0x6245 25157 reserved rw [6:0] reserved 0x45 69 reserved [14:8] reserved 0x62 98 reserved 30 222 reserved 0x6230 25136 reserved rw [6:0] reserved 0x30 48 reserved [14:8] reserved 0x62 98 reserved 31 223 reserved 0x001a 26 reserved rw [6:0] reserved 0x1a 26 reserved 32 224 reserved 0x3e01 15873 reserved rw [3:0] reserved 0x1 1 reserved [7:4] reserved 0x00 0 reserved [8] reserved 0x0 0 reserved [9] reserved 0x1 1 reserved [10] reserved 0x1 1 reserved [11] reserved 0x1 1 reserved [12] reserved 0x1 1 reserved [13] reserved 0x1 1 reserved 33 225 reserved 0x5ef1 24305 reserved rw [4:0] reserved 0x11 17 reserved [9:5] reserved 0x17 23 reserved [14:10] reserved 0x17 23 reserved [15] reserved 0x0 0 reserved 34 226 reserved 0x6000 24576 reserved rw [4:0] reserved 0x00 0 reserved [9:5] reserved 0x00 0 reserved [14:10] reserved 0x18 24 reserved [15] reserved 0x0 0 reserved 35 227 reserved 0x0000 0 reserved rw [0] reserved 0x0 0 reserved [1] reserved 0x0 0 reserved
noip1sn1300a www.onsemi.com 70 table 37. register map address offset type description default default (hex) register name bit field address [2] reserved 0x0 0 reserved [3] reserved 0x0 0 reserved [4] reserved 0x0 0 reserved 36 228 roi_active0_1 0x0001 1 active roi selection rw [7:0] roi_active1[7:0] 0x01 1 roi configuration 37 229 reserved 0x0000 0 reserved rw reserved reserved 38 230 reserved 0x0001 1 reserved rw [15:0] reserved 0x0001 1 reserved 39 231 reserved 0x0000 0 reserved rw [15:0] reserved 0x0000 0 reserved 40 232 reserved 0x0000 0 reserved rw [15:0] reserved 0x0000 0 reserved 41 233 reserved 0x0000 0 reserved rw [15:0] reserved 0x0000 0 reserved 42 234 reserved 0x0000 0 reserved rw [15:0] reserved 0x0000 0 reserved 43 235 reserved 0x01e3 483 reserved rw [4:0] reserved 0x03 3 reserved [12:5] reserved 0xf 15 reserved 44 236 reserved 0x0080 128 reserved rw [11:0] reserved 0x080 128 reserved 45 237 reserved 0x0000 0 reserved rw [15:0] reserved 0x0000 0 reserved 46 238 reserved 0xffff 65535 reserved rw [15:0] reserved 0xffff 65535 reserved 47 239 reserved 0x0000 0 reserved rw [15:0] reserved 0x0 0 reserved 48 240 x_resolution 0x00a0 [0x0068, 0x0054] 160 [104, 84] sequencer status status [7:0] x_resolution 0x00a0 [0x0068, 0x0054] 160 [104, 84] sensor x resolution 49 241 y_resolution 0x0400 [0x0268, 0x01f0] 1024 [616, 496] sequencer status status [12:0] y_resolution 0x0400 [0x0268, 0x01f0] 1024 [616, 496] sensor y resolution 50 242 mult_timer_status 0x0000 0 sequencer status status [15:0] mult_timer 0x0000 0 mult timer status (master snapshot shutter only) 51 243 reset_length_status 0x0000 0 sequencer status status [15:0] reset_length 0x0000 0 current reset length (not in slave mode) 52 244 exposure_status 0x0000 0 sequencer status status [15:0] exposure 0x0000 0 current exposure time (not in slave mode)
noip1sn1300a www.onsemi.com 71 table 37. register map address offset type description default default (hex) register name bit field address 53 245 exposure_ds_status 0x0000 0 sequencer status status [15:0] exposure_ds 0x0000 0 current exposure time (not in slave mode) 54 246 exposure_ts_status 0x0000 0 sequencer status status [15:0] exposure_ts 0x0000 0 current exposure time (not in slave mode) 55 247 gain_status 0x0000 0 sequencer status status [4:0] mux_gainsw 0x00 0 current column gain setting [12:5] afe_gain 0x00 0 current afe programmable gain 56 248 digital_gain_status 0x0000 0 sequencer status status [11:0] db_gain 0x000 0 digital gain [12] dual_slope 0x0 0 dual slope enabled [13] triple_slope 0x0 0 triple slope enabled 58 250 reserved 0x0423 1059 reserved rw [4:0] reserved 0x03 3 reserved [9:5] reserved 0x01 1 reserved [14:10] reserved 0x01 1 reserved 59 251 reserved 0x030f 783 reserved rw [7:0] reserved 0xf 15 reserved [15:8] reserved 0x3 3 reserved 60 252 reserved 0x0601 1537 reserved rw [7:0] reserved 0x1 1 reserved [15:8] reserved 0x6 6 reserved 61 253 roi_aec_configura- tion0 0x0000 0 aec roi configuration rw [7:0] x_start 0x00 0 aec roi x start configuration (used for aec statistics when roi_aec_enable=?1?) [15:8] x_end 0x00 0 aec roi x end configuration (used for aec statistics when roi_aec_enable=?1?) 62 254 roi_aec_configura- tion1 0x0000 0 aec roi configuration rw [12:0] y_start 0x0000 0 aec roi y start configuration (used for aec statistics when roi_aec_enable=?1?) 63 255 roi_aec_configura- tion2 0x0000 0 aec roi configuration rw [12:0] y_end 0x0000 0 aec roi y end configuration (used for aec statistics when roi_aec_enable=?1?) sequencer roi [block offset: 256] 0 256 roi0_configuration0 0x9f00 40704 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x9f 159 x end configuration 1 257 roi0_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 2 258 roi0_configuration2 0x03ff 1023 roi configuration rw [12:0] y_end 0x3ff 1023 y end configuration 3 259 roi1_configuration0 0x9f00 40704 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x9f 159 x end configuration
noip1sn1300a www.onsemi.com 72 table 37. register map address offset type description default default (hex) register name bit field address 4 260 roi1_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 5 261 roi1_configuration2 0x03ff 1023 roi configuration rw [12:0] y_end 0x3ff 1023 y end configuration 6 262 roi2_configuration0 0x9f00 40704 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x9f 159 x end configuration 7 263 roi2_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 8 264 roi2_configuration2 0x03ff 1023 roi configuration rw [12:0] y_end 0x3ff 1023 y end configuration 9 265 roi3_configuration0 0x9f00 40704 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x9f 159 x end configuration 10 266 roi3_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 11 267 roi3_configuration2 0x03ff 1023 roi configuration rw [12:0] y_end 0x3ff 1023 y end configuration 12 268 roi4_configuration0 0x9f00 40704 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x9f 159 x end configuration 13 269 roi4_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 14 270 roi4_configuration2 0x03ff 1023 roi configuration rw [12:0] y_end 0x3ff 1023 y end configuration 15 271 roi5_configuration0 0x9f00 40704 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x9f 159 x end configuration 16 272 roi5_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 17 273 roi5_configuration2 0x03ff 1023 roi configuration rw [12:0] y_end 0x3ff 1023 y end configuration 18 274 roi6_configuration0 0x9f00 40704 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x9f 159 x end configuration 19 275 roi6_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration 20 276 roi6_configuration2 0x03ff 1023 roi configuration rw [12:0] y_end 0x3ff 1023 y end configuration 21 277 roi7_configuration0 0x9f00 40704 roi configuration rw [7:0] x_start 0x00 0 x start configuration [15:8] x_end 0x9f 159 x end configuration 22 278 roi7_configuration1 0x0000 0 roi configuration rw [12:0] y_start 0x0000 0 y start configuration
noip1sn1300a www.onsemi.com 73 table 37. register map address offset type description default default (hex) register name bit field address 23 279 roi7_configuration2 0x03ff 1023 roi configuration rw [12:0] y_end 0x3ff 1023 y end configuration sequencer roi [block offset: 384] 0 384 reserved reserved rw [15:0] reserved reserved .. ? ? ? ? ? 127 511 reserved reserved rw [15:0] reserved reserved
noip1sn1300a www.onsemi.com 74 package information pin list the python 300, python 500, and python 1300 image sensors are available in an lvds output configuration (p1?sn/se/fn, p3?sn/se/fn), with the python 1300 also available in a cmos output configuration (p2?sn/se). the lvds i/os comply to the tia/eia?644?a standard and the cmos i/os have a 3.3 v signal level. tables 38 and 39 show the pin list for both versions. table 38. pin list for p1?sn/se/fn, p3?sn/se/fn lvds interface pack pin no. pin name i/o type direction description 1 vdd_33 supply 3.3 v supply 2 mosi cmos input spi master out ? slave in 3 miso cmos output spi master in ? slave out 4 sck cmos input spi clock 5 gnd_18 supply 1.8 v ground 6 vdd_18 supply 1.8 v supply 7 clock_outn lvds output lvds clock output (negative) 8 clock_outp lvds output lvds clock output (positive) 9 doutn0 lvds output lvds data output channel #0 (negative) 10 doutp0 lvds output lvds data output channel #0 (positive) 11 doutn1 lvds output lvds data output channel #1 (negative). not connected for p3 12 doutp1 lvds output lvds data output channel #1 (positive). not connected for p3 13 doutn2 lvds output lvds data output channel #2 (negative) 14 doutp2 lvds output lvds data output channel #2 (positive) 15 doutn3 lvds output lvds data output channel #3 (negative). not connected for p3 16 doutp3 lvds output lvds data output channel #3 (positive). not connected for p3 17 syncn lvds output lvds sync channel output (negative) 18 syncp lvds output lvds sync channel output (positive) 19 vdd_33 supply 3.3 v supply 20 gnd_33 supply 3.3 v ground 21 gnd_18 supply 1.8 v ground 22 vdd_18 supply 1.8 v supply 23 lvds_clock_inn lvds input lvds clock input (negative) 24 lvds_clock_inp lvds input lvds clock input (positive) 25 clk_pll cmos input reference clock input for pll 26 vdd_18 supply 1.8 v supply 27 gnd_18 supply 1.8 v ground 28 ibias_master analog i/o master bias reference. connect with 47k to gnd_33. 29 vdd_33 supply 3.3 v supply 30 gnd_33 supply 3.3 v ground 31 vdd_pix supply pixel array supply 32 gnd_colpc supply pixel array ground 33 vdd_pix supply pixel array supply 34 gnd_colpc supply pixel array ground 35 gnd_33 supply 3.3 v ground
noip1sn1300a www.onsemi.com 75 table 38. pin list for p1?sn/se/fn, p3?sn/se/fn lvds interface pack pin no. description direction i/o type pin name 36 vdd_33 supply 3.3 v supply 37 gnd_colpc supply pixel array ground 38 vdd_pix supply pixel array supply 39 gnd_colpc supply pixel array ground 40 vdd_pix supply pixel array supply 41 trigger0 cmos input trigger input #0 42 trigger1 cmos input trigger input #1 43 trigger2 cmos input trigger input #2 44 monitor0 cmos output monitor output #0 45 monitor1 cmos output monitor output #1 46 reset_n cmos input sensor reset (active low) 47 ss_n cmos input spi slave select (active low) 48 gnd_33 supply 3.3 v ground table 39. pin list for p2?sn/se cmos interface pack pin no. pin name i/o type direction description 1 vdd_33 supply 3.3 v supply 2 mosi cmos input spi master out ? slave in 3 miso cmos output spi master in ? slave out 4 sck cmos input spi clock 5 gnd_18 supply 1.8 v ground 6 vdd_18 supply 1.8 v supply 7 dout9 cmos output data output bit #9 8 dout8 cmos output data output bit #8 9 dout7 cmos output data output bit #7 10 dout6 cmos output data output bit #6 11 dout5 cmos output data output bit #5 12 dout4 cmos output data output bit #4 13 dout3 cmos output data output bit #3 14 dout2 cmos output data output bit #2 15 dout1 cmos output data output bit #1 16 dout0 cmos output data output bit #0 17 frame_valid cmos output frame valid output 18 line_valid cmos output line valid output 19 vdd_33 supply 3.3 v supply 20 gnd_33 supply 3.3 v ground 21 clk_out cmos clock output 22 vdd_18 supply 1.8 v supply 23 lvds_clock_inn lvds input lvds clock input (negative) 24 lvds_clock_inp lvds input lvds clock input (positive) 25 clk_pll cmos input cmos clock input
noip1sn1300a www.onsemi.com 76 table 39. pin list for p2?sn/se cmos interface pack pin no. description direction i/o type pin name 26 vdd_18 supply 1.8 v supply 27 gnd_18 supply 1.8 v ground 28 ibias_master analog i/o master bias reference. connect with 47k to gnd_33. 29 vdd_33 supply 3.3 v supply 30 gnd_33 supply 3.3 v ground 31 vdd_pix supply pixel array supply 32 gnd_colpc supply pixel array ground 33 vdd_pix supply pixel array supply 34 gnd_colpc supply pixel array ground 35 gnd_33 supply 3.3 v ground 36 vdd_33 supply 3.3 v supply 37 gnd_colpc supply pixel array ground 38 vdd_pix supply pixel array supply 39 gnd_colpc supply pixel array ground 40 vdd_pix supply pixel array supply 41 trigger0 cmos input trigger input #0 42 trigger1 cmos input trigger input #1 43 trigger2 cmos input trigger input #2 44 monitor0 cmos output monitor output #0 45 monitor1 cmos output monitor output #1 46 reset_n cmos input sensor reset (active low) 47 ss_n cmos input spi slave select (active low) 48 gnd_33 supply 3.3 v ground
noip1sn1300a www.onsemi.com 77 table 40. mechanical specification parameter description min typ max units die (refer to figure 54 and figure 55 showing pin 1 reference as left center) die thickness 725 m die size 9.0 x 7.95 mm 2 die center, x offset to the center of package ?50 0 50 m die center, y offset to the center of the package ?225 ?175 ?125 m die position, tilt to the die attach plane ?1 0 1 deg die rotation accuracy (referenced to die scribe and lead fin- gers on package on all four sides) ?1 0 1 deg optical center referenced from the die/package center (x?dir) ?179.24 m optical center referenced from the die center (y?dir) 1542.14 m optical center referenced from the package center (y?dir) 1367.14 m distance from bottom of the package to top of the die surface 1.165 1.260 1.405 mm distance from top of the die surface to top of the glass lid 0.655 0.990 1.305 mm glass lid specification xy size 13.6 x 13.6 mm 2 thickness 0.5 0.55 0.6 mm spectral response range 400 1000 nm transmission of glass lid (refer to figure 53) 92 % glass lid material d263 teco mechanical shock jesd22?b104c; condition g 2000 g vibration jesd22?b103b; condition 1 2000 hz mounting profile reflow profile according to j?std?020d.1 260 c recommended socket andon electronics corporation http://www.andonelect.com 680?48?sm?g10?r14?x cte coefficient of thermal expansion of the lcc package 7.1 m/ c
noip1sn1300a www.onsemi.com 78 package drawing figure 53. package drawing for the 48?pin lcc package glass r.19 1.08 2.28 a a section a?a 1.65 0.55 1.26 cross section view side view
noip1sn1300a www.onsemi.com 79 table 41. optical center information python1300 python500 python300 references* x ( m) y ( m) x ( m) y ( m) x ( m) y ( m) die outer cordinates d1 0 9000 0 9000 0 9000 d2 7950 9000 7950 9000 7950 9000 d3 7950 0 7950 0 7950 0 d4 0 0 0 0 0 0 die center cd 3975 4500 3975 4500 3975 4500 pixel area coordinates a1 704.56 8518.94 704.56 8518.94 704.56 8518.94 a2 6886.96 8518.94 6886.96 8518.94 6886.96 8518.94 a3 6886.96 3565.34 6886.96 3565.34 6886.96 3565.34 a4 704.56 3565.34 704.56 3565.34 704.56 3565.34 active area center aa 3795.76 6042.14 3795.76 6042.14 3795.76 6042.14 pitch 4.8 4.8 4.8 4.8 4.8 4.8 # pixels 1288 1032 1288 1032 1288 1032 # dummy 8 8 456 400 616 520 # active pixels 1280 1024 832 632 672 512 active area coordi- nates act_a1 723.76 8499.74 1798.96 7558.94 2182.96 7270.94 act_a2 6867.76 8499.74 5792.56 7558.94 5408.56 7270.94 act_a3 6867.76 3584.54 5792.56 4525.34 5408.56 4813.34 act_a4 723.76 3584.54 1798.96 4525.34 2182.96 4813.34 *refer to figure 54. figure 54. graphical representation of the optical center for python 1300/500/300 (1 of 2) on 5.31 0.18 10.617 0.13 5.31 0.18 6.93 8.48 10.617 0.13 5 10 15 20 25 30 35 40 45 48 a1 a2 a3 a4 pixel (0.0) aa cc cd 0.175 d1 d2 d4 d3
noip1sn1300a www.onsemi.com 80 figure 55. graphical representation of the optical center (2 of 2) center of optical area pin 1 optical area die pin 2 pixel 0,0 center of package 7.29 6.93 5.74 8.48 0.18 1.37 top view detail e view from bottom side detail d 1.27 1.27 0.51 0.51 1.02 r0.19 center of optical area pin 1 pin 2 d e 5.917 6.275 4.728 7.464 note: dimensions in mm
noip1sn1300a www.onsemi.com 81 packing and tray specification the python packing specification with on semiconductor packing labels is packed as follows: table 42. packing and tray specification clcc package (mm) tray restraint box leads length width thickness* tray spec# quantity / tray strap bag tray quantity 48 14.22 14.22 2.28 ks?87233 64 rubber band double bagged using mbb and pink esd bag 5 trays + 1 cover tray *includes package, glass and glue attach thickness. cover paper to be placed on the top tray. figure 56. packing and tray configuration (1 of 2) note: dimensions in mm (not to scale)
noip1sn1300a www.onsemi.com 82 figure 57. packing and tray configuration (2 of 2) note: dimensions in mm (not to scale)
noip1sn1300a www.onsemi.com 83 glass lid the python 300, python 500, and python 1300 image sensors use a glass lid without any coatings. figure 44 shows the transmission characteristics of the glass lid. as shown in figure 52, no infrared attenuating color filter glass is used. use of an ir cut filter is recommended in the optical path when color devices are used. (source: http://www .pgo?online.com ). figure 58. transmission characteristics of the glass lid protective foil for certain size and speed options, the sensor can be delivered with a protective foil that is intended to be removed after assembly. the dimensions of the foil are as illustrated in figure 59 with the tab ali gned towards pin 1 of the package. figure 59. dimensions of the protective foil (units in mm)
noip1sn1300a www.onsemi.com 84 specifications and useful references the following references are available to customers under nda at the on semiconductor image sensor portal : ? product acceptance criteria ? product qualification report ? python developer?s guide and9362/d material composition is available at http://www.onsemi.com/powersolutions/materialcompos ition.do?searchparts=python1300 useful references for information on esd handling, cover glass care and cleanliness, mounting information, please download the image sensor handling and best practices application note (an52561/d) from www.onsemi.com . for quality and reliability information, please download the quality & reliability handbook (hbd851/d) from www.onsemi.com . for information on standard terms and conditions of sale, please download terms and conditions from www.onsemi.com . for information on acronyms and a glossary of terms used, please download image sensor terminology (tnd6116/d) from www.onsemi.com . return material authorization (rma) refer to the on semiconductor rma policy procedure at http://www.onsemi.com/site/pdf/cat_returns_failurean alysis.pdf on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 noip1sn1300a/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative ?

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